Added config register printing

Cargo.toml

@@ -20,6 +20,7 @@ log = { version = "0.4.8", default-features = false }
 rusb = "0.6.0"
 dataview = "0.1"
 bitfield = "0.13.2"
+pretty-hex = "0.1"
 
 [dev-dependencies]
 clap = "2.33.0"

examples/read_pcileech.rs

@@ -4,7 +4,7 @@ use memflow_core::connector::ConnectorArgs;
 use memflow_pcileech::{create_connector, PcieGen};
 
 fn main() {
-    simple_logger::init_with_level(Level::Trace).unwrap();
+    simple_logger::init_with_level(Level::Debug).unwrap();
     let mut conn = create_connector(&ConnectorArgs::new()).unwrap();
     conn.set_pcie_gen(PcieGen::Gen2).unwrap();
 }

src/fpga.rs

@@ -12,6 +12,7 @@ use memflow_core::{
 
 use bitfield::bitfield;
 use dataview::Pod;
+use pretty_hex::*;
 
 pub const FPGA_CONFIG_CORE: u16 = 0x0003;
 pub const FPGA_CONFIG_PCIE: u16 = 0x0001;
@@ -76,11 +77,9 @@ impl Device {
 
         // check chip configuration
         let mut conf = ft60.config()?;
-        trace!(
+        info!(
             "ft60x config: fifo_mode={} channel_config={} optional_feature={}",
-            conf.fifo_mode,
+            conf.fifo_mode, conf.channel_config, conf.optional_feature_support
-            conf.channel_config,
-            conf.optional_feature_support
         );
 
         if conf.fifo_mode != FifoMode::Mode245 as i8
@@ -226,6 +225,45 @@ impl Device {
         Ok(PhyConfigRd { 0: rd_raw })
     }
 
+    /// Prints out all internal registers of the FPGA to `info!()`
+    /// In detail this will request the core/pcie readonly and read/write registers
+    /// and print them out via `info!()`. This is usually useful when debugging any
+    /// issues with the hardware.
+    pub fn print_registers(&mut self) -> Result<()> {
+        info!(
+            "core read-only registers: {:?}",
+            self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?
+                .hex_dump()
+        );
+        info!(
+            "core read-write registers: {:?}",
+            self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE)?
+                .hex_dump()
+        );
+        info!(
+            "pcie read-only registers: {:?}",
+            self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)?
+                .hex_dump()
+        );
+        info!(
+            "core read-write registers: {:?}",
+            self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)?
+                .hex_dump()
+        );
+        Ok(())
+    }
+
+    fn get_register(&mut self, flags: u16) -> Result<Vec<u8>> {
+        let size = self.read_config::<u16>(0x0004, flags)?;
+        info!(
+            "reading fpga device config register {:x} with a length of {:x} bytes.",
+            flags, size
+        );
+        let mut buf = vec![0u8; size as usize];
+        self.read_config_into_raw(0x0000, &mut buf[..], flags)?;
+        Ok(buf)
+    }
+
     #[allow(clippy::uninit_assumed_init)]
     fn read_config<T: Pod>(&mut self, addr: u16, flags: u16) -> Result<T> {
         let mut obj: T = unsafe { MaybeUninit::uninit().assume_init() };

src/lib.rs

@@ -40,10 +40,13 @@ impl PciLeech {
         device.write_inactivity_timer()?;
 
         let device_id = device.read_devid()?;
+        if device_id.1 == 0 {
+            return Err(Error::Connector("fpga did not find a valid pcie device id"));
+        }
 
         let (wr, rd) = device.get_phy()?;
 
-        // https://github.com/ufrisk/LeechCore/blob/master/leechcore/device_fpga.c#L2133
+        device.print_registers().ok();
 
         Ok(Self {
             device,