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@ -139,49 +139,42 @@ impl PhysicalMemory for PciLeech {
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}
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}
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fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> {
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fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> {
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let handle = self.handle.lock().unwrap();
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for write in data.iter() {
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// for now we just assume all writes are un-aligned as we barely ever write big chunks
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let aligned_address = write.0.address().as_page_aligned(0x1000);
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// unaligned read
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let offset = (write.0.as_u64() - aligned_address.as_u64()) as usize;
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// do we cross a page boundary?
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let page_len = if offset + (write.1.len() % 0x1000) <= 0x1000 {
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Address::from(offset + write.1.len() + 0x1000)
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.as_page_aligned(0x1000)
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.as_usize()
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} else {
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Address::from(offset + write.1.len() + 0x2000)
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.as_page_aligned(0x1000)
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.as_usize()
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};
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// first read in the entire page
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let mut page = vec![0u8; page_len];
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self.phys_read_raw_into(aligned_address.into(), &mut page)?;
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// TODO: everything apart from 0x1000 byte buffers crashes...
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// overwrite parts of the page
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unsafe {
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page[offset..(offset + write.1.len())].copy_from_slice(&write.1);
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for write in data.iter() {
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println!("write at {} with size {}", aligned_address, page.len());
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// write page
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let handle = self.handle.lock().unwrap();
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unsafe {
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LcWrite(
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LcWrite(
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*handle,
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*handle,
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write.0.as_u64(),
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aligned_address.as_u64(),
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write.1.len() as u32,
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page.len() as u32,
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write.1.as_ptr() as *mut u8,
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page.as_ptr() as *mut u8,
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);
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);
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/*
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// TODO: ensure reading just 1 page...
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// TODO: handle page boundaries
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if write.1.len() < 0x1000 {
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let mut page = [0u8; 0x1000];
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let aligned = write.0.address().as_page_aligned(0x1000);
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unsafe {
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LcRead(
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self.handle,
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aligned.as_u64(),
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page.len() as u32,
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page.as_mut_ptr(),
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)
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};
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let offs = (read.0.as_u64() - aligned.as_u64()) as usize;
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read.1.copy_from_slice(
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&page[offs..offs+read.1.len()],
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);
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} else {
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// TODO: handle multiple pages at once
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// TODO: handle page alignment
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unsafe {
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LcRead(
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self.handle,
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read.0.as_u64(),
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read.1.len() as u32,
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read.1.as_mut_ptr(),
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)
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};
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}
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*/
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}
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}
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}
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}
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Ok(())
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Ok(())
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