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41 lines
884 B
Coq
41 lines
884 B
Coq
8 months ago
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// 该模块是把通过串口接收到的数据, 通过 uart_rx模块 把串行数据转为并行, 并保存到 rx_data中
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// 接收一帧之后 拉高rx_done, rx_done和uart_tx模块的start_en相连,通过uart_tx模块再原封不动的把rx_data中的并行数据, 通过txd 再发送出去
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module uart_top(
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input wire sys_clk, // U18
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input wire sys_rst, //J15
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input wire rxd,
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output wire txd
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);
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parameter CLK_FREQ = 5000_0000;
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parameter BPS = 115200;
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wire rx_done;
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wire [7:0] rx_data;
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uart_rx #(
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.CLK_FREQ(CLK_FREQ),
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.BPS(BPS)
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)u_uart_rx(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.rxd(rxd),
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.rx_done(rx_done),
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.rx_data(rx_data)
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);
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uart_tx #(
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.CLK_FREQ(CLK_FREQ),
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.BPS(BPS)
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)u_uart_tx(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.start_en(rx_done),
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.tx_data(rx_data),
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.txd(txd),
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.tx_busy()
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);
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endmodule
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