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verilog_stu
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verilog_stu/uart
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阳光少年 3816e69714 优化代码, 防止发送过快或者晶振导致计数器误差, start_en在busy结束之前出现导致计数器不再工作 1 year ago
..
rx_时序图.png uart的接收模块完成 1 year ago
tb_uart.v 仿真通过 1 year ago
tx_时序图.png 仿真通过 1 year ago
uart_rx.v 仿真通过 1 year ago
uart_rx.v.out uart的接收模块完成 1 year ago
uart_top.v 仿真通过 1 year ago
uart_tx.v 优化代码, 防止发送过快或者晶振导致计数器误差, start_en在busy结束之前出现导致计数器不再工作 1 year ago
uart_tx.v.out 优化代码, 防止发送过快或者晶振导致计数器误差, start_en在busy结束之前出现导致计数器不再工作 1 year ago
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