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verilog_stu
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37b49b3c7f
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verilog_stu
/
dip
/
dip.v
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增加一个dip控制
8 months ago
module
dip
(
input
dip1
,
//
f20
修改bug
8 months ago
output
led
//
g14
增加一个dip控制
8 months ago
)
;
assign
led
=
!
dip1
;
endmodule