增加一个dip控制
parent
b060b596cd
commit
c223828a2b
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module dip(
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input dip1, // f20
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input led // g14
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);
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assign led = !dip1;
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endmodule
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#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
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:ivl_version "12.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
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S_0x7fa85fb046a0 .scope module, "dip" "dip" 2 1;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "dip1";
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.port_info 1 /INPUT 1 "led";
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o0x7fa85fa32008 .functor BUFZ 1, C4<z>; HiZ drive
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v0x7fa85fb04840_0 .net "dip1", 0 0, o0x7fa85fa32008; 0 drivers
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v0x7fa85fb148b0_0 .net "led", 0 0, L_0x7fa85ef05c70; 1 drivers
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L_0x7fa85ef05c70 .reduce/nor o0x7fa85fa32008;
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# The file index is used to find the file name in the following table.
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:file_names 3;
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"N/A";
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"<interactive>";
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"dip.v";
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