完事单端口ram读取写入实验
阳光少年
8 months ago
parent
9a85504756
commit
3eaadf2bd6
@ -0,0 +1,75 @@
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`timescale 1ns/1ns
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module tb_ram();
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reg sys_clk;
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reg sys_rst;
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always #10 sys_clk = ~sys_clk;
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initial begin
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sys_clk <= 1'b0;
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sys_rst <= 1'b0;
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#50
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sys_rst <= 1'b1;
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end
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reg ram_en;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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ram_en <= 1'b0;
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end
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// 只有在复位之后, 才允许启动ram
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else begin
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ram_en <= 1'b1;
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end
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end
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reg [7:0]counter; // 计数到15 清零, 变化范围 0~15
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wire ram_rw;
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assign ram_rw = ram_en && (counter <= 8'b111); // 计数器 分成读写各占一半时间, 0~7的时候高电平进行写, 8~15低电平进行读取
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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counter <= 8'b0;
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end
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// 没有启用ram禁止计数
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else if (ram_en == 1'b0 || counter == 8'b1111) begin
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counter <= 8'b0;
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end
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else begin
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counter <= counter + 8'b1;
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end
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end
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reg [2:0]ram_data; // 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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ram_data <= 3'b0;
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end
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// 如果是写, 并且还没到最大数
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else if (ram_rw && ram_data < 3'b111) begin
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ram_data <= ram_data + 3'b1;
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end
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else begin
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ram_data <= 3'b0;
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end
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end
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reg [2:0]ram_addr; // 地址变化范围 0~7就行了
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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ram_addr <= 3'b0;
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end
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// 没有启用ram禁止计数
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else if (ram_en == 1'b0 && ram_addr == 3'b111) begin
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ram_addr <= 3'b0;
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end
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else begin
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ram_addr <= ram_addr + 3'b1;
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end
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end
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endmodule
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@ -0,0 +1,153 @@
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#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
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:ivl_version "12.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 9;
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
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S_0x7fe52f706430 .scope module, "tb_ram" "tb_ram" 2 2;
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.timescale -9 -9;
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L_0x7fe52f716d40 .functor AND 1, v0x7fe52f716950_0, L_0x7fe52f716c60, C4<1>, C4<1>;
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L_0x7fe530163008 .functor BUFT 1, C4<00000111>, C4<0>, C4<0>, C4<0>;
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v0x7fe52f7065b0_0 .net/2u *"_ivl_0", 7 0, L_0x7fe530163008; 1 drivers
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v0x7fe52f716670_0 .net *"_ivl_2", 0 0, L_0x7fe52f716c60; 1 drivers
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v0x7fe52f716710_0 .var "counter", 7 0;
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v0x7fe52f7167b0_0 .var "ram_addr", 2 0;
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v0x7fe52f716860_0 .var "ram_data", 2 0;
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v0x7fe52f716950_0 .var "ram_en", 0 0;
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v0x7fe52f7169f0_0 .net "ram_rw", 0 0, L_0x7fe52f716d40; 1 drivers
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v0x7fe52f716a90_0 .var "sys_clk", 0 0;
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v0x7fe52f716b30_0 .var "sys_rst", 0 0;
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E_0x7fe52f706320/0 .event negedge, v0x7fe52f716b30_0;
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E_0x7fe52f706320/1 .event posedge, v0x7fe52f716a90_0;
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E_0x7fe52f706320 .event/or E_0x7fe52f706320/0, E_0x7fe52f706320/1;
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L_0x7fe52f716c60 .cmp/ge 8, L_0x7fe530163008, v0x7fe52f716710_0;
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.scope S_0x7fe52f706430;
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T_0 ;
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%delay 10, 0;
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%load/vec4 v0x7fe52f716a90_0;
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%inv;
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%store/vec4 v0x7fe52f716a90_0, 0, 1;
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%jmp T_0;
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.thread T_0;
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.scope S_0x7fe52f706430;
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T_1 ;
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%wait E_0x7fe52f706320;
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%load/vec4 v0x7fe52f716b30_0;
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%nor/r;
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%flag_set/vec4 8;
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%jmp/0xz T_1.0, 8;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fe52f716950_0, 0;
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%jmp T_1.1;
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T_1.0 ;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x7fe52f716950_0, 0;
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T_1.1 ;
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%jmp T_1;
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.thread T_1;
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.scope S_0x7fe52f706430;
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T_2 ;
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%wait E_0x7fe52f706320;
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%load/vec4 v0x7fe52f716b30_0;
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%nor/r;
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%flag_set/vec4 8;
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%jmp/0xz T_2.0, 8;
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%pushi/vec4 0, 0, 8;
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%assign/vec4 v0x7fe52f716710_0, 0;
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%jmp T_2.1;
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T_2.0 ;
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%load/vec4 v0x7fe52f716950_0;
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%cmpi/e 0, 0, 1;
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%jmp/1 T_2.4, 4;
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%flag_mov 8, 4;
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%load/vec4 v0x7fe52f716710_0;
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%cmpi/e 15, 0, 8;
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%flag_or 4, 8;
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T_2.4;
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%jmp/0xz T_2.2, 4;
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%pushi/vec4 0, 0, 8;
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%assign/vec4 v0x7fe52f716710_0, 0;
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%jmp T_2.3;
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T_2.2 ;
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%load/vec4 v0x7fe52f716710_0;
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%addi 1, 0, 8;
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%assign/vec4 v0x7fe52f716710_0, 0;
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T_2.3 ;
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T_2.1 ;
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%jmp T_2;
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.thread T_2;
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.scope S_0x7fe52f706430;
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T_3 ;
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%wait E_0x7fe52f706320;
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%load/vec4 v0x7fe52f716b30_0;
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%nor/r;
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%flag_set/vec4 8;
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%jmp/0xz T_3.0, 8;
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%pushi/vec4 0, 0, 3;
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%assign/vec4 v0x7fe52f716860_0, 0;
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%jmp T_3.1;
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T_3.0 ;
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%load/vec4 v0x7fe52f7169f0_0;
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%flag_set/vec4 9;
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%flag_get/vec4 9;
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%jmp/0 T_3.4, 9;
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%load/vec4 v0x7fe52f716860_0;
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%cmpi/u 7, 0, 3;
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%flag_get/vec4 5;
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%and;
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T_3.4;
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%flag_set/vec4 8;
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%jmp/0xz T_3.2, 8;
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%load/vec4 v0x7fe52f716860_0;
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%addi 1, 0, 3;
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%assign/vec4 v0x7fe52f716860_0, 0;
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%jmp T_3.3;
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T_3.2 ;
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%pushi/vec4 0, 0, 3;
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%assign/vec4 v0x7fe52f716860_0, 0;
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T_3.3 ;
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T_3.1 ;
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%jmp T_3;
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.thread T_3;
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.scope S_0x7fe52f706430;
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T_4 ;
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%wait E_0x7fe52f706320;
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%load/vec4 v0x7fe52f716b30_0;
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%nor/r;
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%flag_set/vec4 8;
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%jmp/0xz T_4.0, 8;
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%pushi/vec4 0, 0, 3;
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%assign/vec4 v0x7fe52f7167b0_0, 0;
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%jmp T_4.1;
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T_4.0 ;
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%load/vec4 v0x7fe52f716950_0;
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%cmpi/e 0, 0, 1;
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%flag_get/vec4 4;
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%jmp/0 T_4.4, 4;
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%load/vec4 v0x7fe52f7167b0_0;
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%pushi/vec4 7, 0, 3;
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%cmp/e;
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%flag_get/vec4 4;
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%and;
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T_4.4;
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%flag_set/vec4 8;
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%jmp/0xz T_4.2, 8;
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%pushi/vec4 0, 0, 3;
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%assign/vec4 v0x7fe52f7167b0_0, 0;
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%jmp T_4.3;
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T_4.2 ;
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%load/vec4 v0x7fe52f7167b0_0;
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%addi 1, 0, 3;
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%assign/vec4 v0x7fe52f7167b0_0, 0;
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T_4.3 ;
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T_4.1 ;
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%jmp T_4;
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.thread T_4;
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# The file index is used to find the file name in the following table.
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:file_names 3;
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"N/A";
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"<interactive>";
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"tb_ram.v";
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