仿真成功

main
阳光少年 8 months ago
parent 3eb9fc25f7
commit 563a00e8d9

@ -0,0 +1,135 @@
`timescale 1ns/1ns
module tb_lm();
reg k_1; // 1
reg k_2; // 2
reg key; // , ,
reg key_1; //
reg key_2; //
reg is_show; //
reg flag; // 500ns,
reg sys_clk;
reg sys_rst;
always #10 sys_clk = ~sys_clk;
initial begin
sys_clk <= 1'b0;
sys_rst <= 1'b0;
#200
sys_rst <= 1'b1;
// 2000, x 0
#2000
// key, 188
key <= 1'b1;
#188
key <= 1'b0;
#400
// 4000
{k_2, k_1} <= 2'b10;
#3900
{k_2, k_1} <= 2'b01;
#3800
// key, 288, , x0
key <= 1'b1;
#288
key <= 1'b0;
end
reg [5:0] CNT;
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
CNT <= 5'd0;
end
else if (CNT < (5'd25 - 5'd1)) begin
CNT <= CNT + 5'd1;
end
else begin
CNT <= 5'b0;
end
end
reg [7:0]x;
reg [7:0]y;
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
{k_2, k_1} <= 2'b11;
x <= 8'b00000000;
y <= 8'b11111111; //
end
else if ({k_2, k_1} == 2'b10 && is_show) begin
case (flag)
1'b0: x <= 8'b1010_1010;
1'b1: x <= 8'b0101_0101;
endcase
end
else if ({k_2, k_1} == 2'b01 && is_show) begin
case (flag)
1'b0: x <= 8'b1111_0000;
1'b1: x <= 8'b0000_1111;
endcase
end
else begin
x <= 8'b00000000;
end
end
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
flag <= 1'b0;
end
else if (CNT == (5'd25 - 5'd1)) begin
flag <= !flag;
end
else begin
end
end
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
key <= 1'b0;
key_1 <= 1'b0;
key_2 <= 1'b0;
end
else begin
key_1 <= key;
key_2 <= key_1;
end
end
// 沿,
assign is_click = key_1 && !key_2;
// 使
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
is_show <= 1'b0;
end
else if (is_click) begin
is_show <= !is_show;
end
else begin
end
end
lm u_lm(
.x (x),
.y (y)
);
endmodule
Loading…
Cancel
Save