优化设计

main
阳光少年 8 months ago
parent 430f88e7be
commit a768bb0fc2

@ -151,9 +151,10 @@ always @(posedge sys_clk or negedge sys_rst) begin
end end
reg [4:0] click_time; // max: 20 reg [4:0] click_time; // max: 20
reg is_down; // ,
always @(posedge sys_clk or negedge sys_rst) begin always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin if (sys_rst == 1'b0) begin
is_show <= 1'b0; is_down <= 1'b0;
click_time <= 5'd0; click_time <= 5'd0;
end end
@ -163,12 +164,8 @@ always @(posedge sys_clk or negedge sys_rst) begin
else begin else begin
// 20 // 20
if (click_time == (5'd20 - 5'd1)) begin if (click_time == (5'd20 - 5'd1)) begin
// key // key, is_down
if (key_1) begin is_down <= key_1;
is_show <= !is_show;
end
else begin
end
end end
else begin else begin
click_time <= click_time + 5'd1; click_time <= click_time + 5'd1;
@ -177,6 +174,32 @@ always @(posedge sys_clk or negedge sys_rst) begin
end end
//
wire is_click;
reg is_down_1;
reg is_down_2;
assign is_click = is_down_1 && !is_down_2;
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
is_down_1 <= 1'b0;
is_down_2 <= 1'b0;
end
else begin
is_down_1 <= is_down;
is_down_2 <= is_down_1;
end
end
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
is_show <= 1'b0;
end
else if (is_click) begin
is_show <= !is_show;
end
else begin
end
end
lm u_lm( lm u_lm(
.x (x), .x (x),

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