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现在使用case进行设计数码管

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阳光少年 8 months ago
parent d5cb5c11f4
commit ddafe17922
3 changed files with 125 additions and 127 deletions
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86
digital_tube/dt.v
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@ -2,50 +2,78 @@
// 7 8 9 10 11 12 6 5 4 3 2 1
// B S3 S2 F A S1 S4 G C DP D E
module dt(
// input wire [7:0]data, // en: 1, select:2, dp: 1, data: 4
output wire A, B, C, D, E, F, G, DP,
output wire S1, S2, S3, S4
input wire [7:0]data, // en: 1, select:2, dp: 1, data: 4
output reg A, B, C, D, E, F, G, DP,
output reg S1, S2, S3, S4
);
wire [7:0]data;
assign data = 8'b1000_0010;
parameter _SELECT_1 = 4'b1110;
parameter _SELECT_2 = 4'b1101;
parameter _SELECT_3 = 4'b1011;
parameter _SELECT_4 = 4'b0111;
parameter SELECTOR = {_SELECT_4, _SELECT_3, _SELECT_2, _SELECT_1};
// parameter SELECTOR = {_SELECT_4, _SELECT_3, _SELECT_2, _SELECT_1};
// ABCD_EFGP
parameter _SHOW_0 = 8'B1111_1110;
parameter _SHOW_1 = 8'B0110_0000;
parameter _SHOW_2 = 8'B1101_1010;
parameter _SHOW_3 = 8'B1111_0010;
parameter _SHOW_4 = 8'B0110_0110;
parameter _SHOW_5 = 8'B1111_1110;
parameter _SHOW_6 = 8'B1111_1110;
parameter _SHOW_7 = 8'B1111_1110;
parameter _SHOW_8 = 8'B1111_1110;
parameter _SHOW_9 = 8'B1111_1110;
parameter _SHOW_A = 8'B1111_1110;
parameter _SHOW_B = 8'B1111_1110;
parameter _SHOW_C = 8'B1111_1110;
parameter _SHOW_D = 8'B1111_1110;
parameter _SHOW_E = 8'B1111_1110;
parameter _SHOW_F = 8'B1111_1110;
// ABCDEFG
parameter _SHOW_0 = 8'B1111111;
parameter _SHOW_1 = 8'B0110000;
parameter _SHOW_2 = 8'B1101101;
parameter _SHOW_3 = 8'B1111001;
parameter _SHOW_4 = 8'B0110011;
parameter _SHOW_5 = 8'B1111111;
parameter _SHOW_6 = 8'B1111111;
parameter _SHOW_7 = 8'B1111111;
parameter _SHOW_8 = 8'B1111111;
parameter _SHOW_9 = 8'B1111111;
parameter _SHOW_A = 8'B1111111;
parameter _SHOW_B = 8'B1111111;
parameter _SHOW_C = 8'B1111111;
parameter _SHOW_D = 8'B1111111;
parameter _SHOW_E = 8'B1111111;
parameter _SHOW_F = 8'B1111111;
parameter SHOW = {_SHOW_F, _SHOW_E, _SHOW_D, _SHOW_C, _SHOW_B, _SHOW_A, _SHOW_9, _SHOW_8, _SHOW_7, _SHOW_6, _SHOW_5, _SHOW_4, _SHOW_3, _SHOW_2, _SHOW_1, _SHOW_0};
// parameter SHOW = {_SHOW_F, _SHOW_E, _SHOW_D, _SHOW_C, _SHOW_B, _SHOW_A, _SHOW_9, _SHOW_8, _SHOW_7, _SHOW_6, _SHOW_5, _SHOW_4, _SHOW_3, _SHOW_2, _SHOW_1, _SHOW_0};
// always @(data) begin
// if (data[7]) begin
// {S4, S3, S2, S1} = SELECTOR >> (data[6:5] << 2);
// {A, B, C, D, E, F, G, DP} = {SHOW >> (data[3:0] << 3) >> 1, data[4]};
// {S4, S3, S2, S1} = SELECTOR >> (data[6:5] * 4);
// {A, B, C, D, E, F, G, DP} = {((SHOW >> (data[3:0] * 7))), data[4]};
// {A, B, C, D, E, F, G, DP} = {SHOW[(data[3:0] * 7)+:7], data[4]};
// end
// end
assign {S4, S3, S2, S1} = 4'b0110;
assign {A, B, C, D, E, F, G, DP} = _SHOW_2;
always @(data) begin
DP = data[4];
case (data[3:0])
4'b0000: {A, B, C, D, E, F, G} = _SHOW_0;
4'b0001: {A, B, C, D, E, F, G} = _SHOW_1;
4'b0010: {A, B, C, D, E, F, G} = _SHOW_2;
4'b0011: {A, B, C, D, E, F, G} = _SHOW_3;
4'b0100: {A, B, C, D, E, F, G} = _SHOW_4;
4'b0101: {A, B, C, D, E, F, G} = _SHOW_5;
4'b0110: {A, B, C, D, E, F, G} = _SHOW_6;
4'b0111: {A, B, C, D, E, F, G} = _SHOW_7;
4'b1000: {A, B, C, D, E, F, G} = _SHOW_8;
4'b1001: {A, B, C, D, E, F, G} = _SHOW_9;
4'b1010: {A, B, C, D, E, F, G} = _SHOW_A;
4'b1011: {A, B, C, D, E, F, G} = _SHOW_B;
4'b1100: {A, B, C, D, E, F, G} = _SHOW_C;
4'b1101: {A, B, C, D, E, F, G} = _SHOW_D;
4'b1110: {A, B, C, D, E, F, G} = _SHOW_E;
4'b1111: {A, B, C, D, E, F, G} = _SHOW_F;
default: ;
endcase
case (data[7:5])
3'b000: {S4, S3, S2, S1} = _SELECT_1;
3'b001: {S4, S3, S2, S1} = _SELECT_2;
3'b010: {S4, S3, S2, S1} = _SELECT_3;
3'b011: {S4, S3, S2, S1} = _SELECT_4;
default: {S4, S3, S2, S1} = 4'b1111;
endcase
end
endmodule

160
digital_tube/dt.v.out
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@ -1,13 +1,13 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_00000211cef464a0 .scope module, "dt" "dt" 2 4;
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
S_0x7ff79e706d30 .scope module, "dt" "dt" 2 4;
.timescale 0 0;
.port_info 0 /INPUT 8 "data";
.port_info 1 /OUTPUT 1 "A";
@ -22,103 +22,73 @@ S_00000211cef464a0 .scope module, "dt" "dt" 2 4;
.port_info 10 /OUTPUT 1 "S2";
.port_info 11 /OUTPUT 1 "S3";
.port_info 12 /OUTPUT 1 "S4";
P_00000211cee05740 .param/l "SELECTOR" 0 2 15, C4<0111101111011110>;
P_00000211cee05778 .param/l "SHOW" 0 2 36, C4<11111110111111101111111011111110111111101111111011111110111111101111111011111110111111100110011011110010110110100110000011111110>;
P_00000211cee057b0 .param/l "_SELECT_1" 0 2 10, C4<1110>;
P_00000211cee057e8 .param/l "_SELECT_2" 0 2 11, C4<1101>;
P_00000211cee05820 .param/l "_SELECT_3" 0 2 12, C4<1011>;
P_00000211cee05858 .param/l "_SELECT_4" 0 2 13, C4<0111>;
P_00000211cee05890 .param/l "_SHOW_0" 0 2 28, C4<11111110>;
P_00000211cee058c8 .param/l "_SHOW_1" 0 2 19, C4<01100000>;
P_00000211cee05900 .param/l "_SHOW_2" 0 2 20, C4<11011010>;
P_00000211cee05938 .param/l "_SHOW_3" 0 2 21, C4<11110010>;
P_00000211cee05970 .param/l "_SHOW_4" 0 2 22, C4<01100110>;
P_00000211cee059a8 .param/l "_SHOW_5" 0 2 23, C4<11111110>;
P_00000211cee059e0 .param/l "_SHOW_6" 0 2 24, C4<11111110>;
P_00000211cee05a18 .param/l "_SHOW_7" 0 2 25, C4<11111110>;
P_00000211cee05a50 .param/l "_SHOW_8" 0 2 26, C4<11111110>;
P_00000211cee05a88 .param/l "_SHOW_9" 0 2 27, C4<11111110>;
P_00000211cee05ac0 .param/l "_SHOW_A" 0 2 29, C4<11111110>;
P_00000211cee05af8 .param/l "_SHOW_B" 0 2 30, C4<11111110>;
P_00000211cee05b30 .param/l "_SHOW_C" 0 2 31, C4<11111110>;
P_00000211cee05b68 .param/l "_SHOW_D" 0 2 32, C4<11111110>;
P_00000211cee05ba0 .param/l "_SHOW_E" 0 2 33, C4<11111110>;
P_00000211cee05bd8 .param/l "_SHOW_F" 0 2 34, C4<11111110>;
v00000211cef46b40_0 .var "A", 0 0;
v00000211cef46710_0 .var "B", 0 0;
v00000211cee144b0_0 .var "C", 0 0;
v00000211cee14550_0 .var "D", 0 0;
v00000211cee145f0_0 .var "DP", 0 0;
v00000211cee5d420_0 .var "E", 0 0;
v00000211cee5d4c0_0 .var "F", 0 0;
v00000211cee5d560_0 .var "G", 0 0;
v00000211cee5d600_0 .var "S1", 0 0;
v00000211cee5d730_0 .var "S2", 0 0;
v00000211cee5d7d0_0 .var "S3", 0 0;
v00000211cee5d870_0 .var "S4", 0 0;
o00000211cee1a1e8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v00000211cee5d910_0 .net "data", 7 0, o00000211cee1a1e8; 0 drivers
E_00000211cee188d0 .event anyedge, v00000211cee5d910_0;
.scope S_00000211cef464a0;
P_0x7ff79e808e00 .param/l "SELECTOR" 0 2 15, C4<0111101111011110>;
P_0x7ff79e808e40 .param/l "SHOW" 0 2 37, C4<01111111011111110111111101111111011111110111111101111111011111110111111101111111011111110011001101111001011011010011000001111111>;
P_0x7ff79e808e80 .param/l "_SELECT_1" 0 2 10, C4<1110>;
P_0x7ff79e808ec0 .param/l "_SELECT_2" 0 2 11, C4<1101>;
P_0x7ff79e808f00 .param/l "_SELECT_3" 0 2 12, C4<1011>;
P_0x7ff79e808f40 .param/l "_SELECT_4" 0 2 13, C4<0111>;
P_0x7ff79e808f80 .param/l "_SHOW_0" 0 2 19, C4<01111111>;
P_0x7ff79e808fc0 .param/l "_SHOW_1" 0 2 20, C4<00110000>;
P_0x7ff79e809000 .param/l "_SHOW_2" 0 2 21, C4<01101101>;
P_0x7ff79e809040 .param/l "_SHOW_3" 0 2 22, C4<01111001>;
P_0x7ff79e809080 .param/l "_SHOW_4" 0 2 23, C4<00110011>;
P_0x7ff79e8090c0 .param/l "_SHOW_5" 0 2 24, C4<01111111>;
P_0x7ff79e809100 .param/l "_SHOW_6" 0 2 25, C4<01111111>;
P_0x7ff79e809140 .param/l "_SHOW_7" 0 2 26, C4<01111111>;
P_0x7ff79e809180 .param/l "_SHOW_8" 0 2 27, C4<01111111>;
P_0x7ff79e8091c0 .param/l "_SHOW_9" 0 2 28, C4<01111111>;
P_0x7ff79e809200 .param/l "_SHOW_A" 0 2 29, C4<01111111>;
P_0x7ff79e809240 .param/l "_SHOW_B" 0 2 30, C4<01111111>;
P_0x7ff79e809280 .param/l "_SHOW_C" 0 2 31, C4<01111111>;
P_0x7ff79e8092c0 .param/l "_SHOW_D" 0 2 32, C4<01111111>;
P_0x7ff79e809300 .param/l "_SHOW_E" 0 2 33, C4<01111111>;
P_0x7ff79e809340 .param/l "_SHOW_F" 0 2 34, C4<01111111>;
v0x7ff79e707690_0 .var "A", 0 0;
v0x7ff79e717740_0 .var "B", 0 0;
v0x7ff79e7177e0_0 .var "C", 0 0;
v0x7ff79e717870_0 .var "D", 0 0;
v0x7ff79e717910_0 .var "DP", 0 0;
v0x7ff79e7179f0_0 .var "E", 0 0;
v0x7ff79e717a90_0 .var "F", 0 0;
v0x7ff79e717b30_0 .var "G", 0 0;
v0x7ff79e717bd0_0 .var "S1", 0 0;
v0x7ff79e717ce0_0 .var "S2", 0 0;
v0x7ff79e717d70_0 .var "S3", 0 0;
v0x7ff79e717e10_0 .var "S4", 0 0;
o0x7ff79f332248 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v0x7ff79e717eb0_0 .net "data", 7 0, o0x7ff79f332248; 0 drivers
E_0x7ff79e707650 .event anyedge, v0x7ff79e717eb0_0;
.scope S_0x7ff79e706d30;
T_0 ;
%wait E_00000211cee188d0;
%load/vec4 v00000211cee5d910_0;
%parti/s 1, 7, 4;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 15, 0, 4;
%split/vec4 1;
%assign/vec4 v00000211cee5d600_0, 0;
%split/vec4 1;
%assign/vec4 v00000211cee5d730_0, 0;
%split/vec4 1;
%assign/vec4 v00000211cee5d7d0_0, 0;
%assign/vec4 v00000211cee5d870_0, 0;
%wait E_0x7ff79e707650;
%load/vec4 v0x7ff79e717eb0_0;
%parti/s 4, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
%jmp/1 T_0.0, 6;
%jmp T_0.1;
T_0.0 ;
%pushi/vec4 14, 0, 4;
%pushi/vec4 127, 0, 8;
%split/vec4 1;
%assign/vec4 v00000211cee5d600_0, 0;
%store/vec4 v0x7ff79e717910_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee5d730_0, 0;
%store/vec4 v0x7ff79e717b30_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee5d7d0_0, 0;
%assign/vec4 v00000211cee5d870_0, 0;
T_0.1 ;
%pushi/vec4 4278124286, 0, 32;
%concati/vec4 4278124286, 0, 32;
%concati/vec4 4278124134, 0, 32;
%concati/vec4 4074397950, 0, 32;
%load/vec4 v00000211cee5d910_0;
%parti/s 4, 0, 2;
%ix/load 5, 3, 0;
%flag_set/imm 4, 0;
%shiftl 5;
%ix/vec4 4;
%shiftr 4;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%load/vec4 v00000211cee5d910_0;
%parti/s 1, 4, 4;
%concat/vec4; draw_concat_vec4
%pad/u 8;
%store/vec4 v0x7ff79e717a90_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee145f0_0, 0;
%store/vec4 v0x7ff79e7179f0_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee5d560_0, 0;
%store/vec4 v0x7ff79e717870_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee5d4c0_0, 0;
%store/vec4 v0x7ff79e7177e0_0, 0, 1;
%split/vec4 1;
%assign/vec4 v00000211cee5d420_0, 0;
%split/vec4 1;
%assign/vec4 v00000211cee14550_0, 0;
%split/vec4 1;
%assign/vec4 v00000211cee144b0_0, 0;
%split/vec4 1;
%assign/vec4 v00000211cef46710_0, 0;
%assign/vec4 v00000211cef46b40_0, 0;
%store/vec4 v0x7ff79e717740_0, 0, 1;
%store/vec4 v0x7ff79e707690_0, 0, 1;
%jmp T_0.1;
T_0.1 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
# The file index is used to find the file name in the following table.

6
led/led_1.v
Unescape Escape View File

@ -3,8 +3,8 @@ module led( // 该括号内对 io口 以及类型 进行说明
output reg led // 因为需要再always中改变状态, 需要设置为寄存器型
);
parameter WIDTH = 5; // 定义一个内部常量, 可以供模块式用, 当然你这个变量可以在外部被修改, 编译的时候使用
parameter WIDTH = 5; // 定义一个内部常量, 可以供模块式用, 当然你这个变量可以在外部被修改, 编译的时候使用, 默认情况下会采用从高位到低位的顺序
parameter [4:0]a_1 = 4'b1010; // 默认的顺序, 注意, a_1 和a_2 内部的值是完全相同, 只是内部的布局不一样
wire [WIDTH:0] tmp1, tmp2; // 定义两个 线类型信号, 宽度为 常量 WIDTH
@ -91,7 +91,7 @@ wire [16:0] Slice;
// 拼接运算符
// 拼接运算符必须要写位宽!! {A[0], 5} 后面的5没有写位宽是禁止的 因为默认是32位或者不知道多少位拼接在一起了
// 拼接运算符右值必须要写位宽!! {A[0], 5} 后面的5没有写位宽是禁止的 因为默认是32位或者不知道多少位拼接在一起了

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