yanguangshaonian
/
verilog_stu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
14 Commits
1 Branch
0 Tags
4.6 MiB
SystemVerilog 67.9%
Verilog 22%
C 10.1%
 
 
 
main
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'ddafe17922'
${ noResults }
Go to file
阳光少年 ddafe17922 现在使用case进行设计数码管 12 months ago
.vscode 增加一下项目文件 12 months ago
38decoder 仓库整理 12 months ago
digital_tube 现在使用case进行设计数码管 12 months ago
dip 添加一些学习注释 12 months ago
led 现在使用case进行设计数码管 12 months ago
README.md Initial commit 12 months ago

README.md

verilog_stu