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56 lines
807 B
Verilog
56 lines
807 B
Verilog
`timescale 1ns/1ns
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module tb_uart();
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reg sys_clk;
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reg sys_rst;
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reg rxd;
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wire txd;
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always #10 sys_clk = ~sys_clk;
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// 发送数据 8'b0101_0101
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parameter [7:0]data = 8'b0101_0101;
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initial begin
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sys_clk <= 1'b0;
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rxd <= 1'b1;
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sys_rst <= 1'b0;
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#50
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sys_rst <= 1'b1;
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#1000
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// 开始发送数据
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rxd <= 1'b0; // 起始位
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#8680
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rxd <= data[0];
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#8680
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rxd <= data[1];
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#8680
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rxd <= data[2];
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#8680
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rxd <= data[3];
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#8680
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rxd <= data[4];
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#8680
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rxd <= data[5];
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#8680
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rxd <= data[6];
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#8680
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rxd <= data[7];
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#8680
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rxd <= 1'b1; // 停止位
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#8680
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rxd <= 1'b1; // 空闲了
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end
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uart_top u_uart_top(
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.sys_clk(sys_clk), // U18
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.sys_rst(sys_rst), //J15
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.rxd(rxd),
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.txd(txd)
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);
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endmodule |