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24 lines
365 B
Verilog
24 lines
365 B
Verilog
`timescale 1ns/1ns
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module tb_clk_wiz();
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reg sys_clk;
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reg sys_rst;
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always #10 sys_clk = ~sys_clk;
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wire clk_100m;
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wire clk_100m_r;
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wire clk_50m;
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wire clk_25m;
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clk_wiz u_clk_wiz(
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.sys_clk(sys_clk), // U18
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.sys_rst(sys_rst), //J15
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.clk_100m(clk_100m),
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.clk_100m_r(clk_100m_r), // 180度
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.clk_50m(clk_50m),
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.clk_25m(clk_25m)
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);
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endmodule
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