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verilog_stu
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SystemVerilog 67.9%
Verilog 22%
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阳光少年 c223828a2b 增加一个dip控制 8 months ago
.vscode 增加一下项目文件 8 months ago
38decoder 仓库整理 8 months ago
dip 增加一个dip控制 8 months ago
led 仓库文件整理 8 months ago
README.md Initial commit 8 months ago

README.md

verilog_stu