verilog_stu/ip_1_port_ram/tb_ram.v

`timescale 1ns/1ns
module tb_ram();

reg sys_clk;
reg sys_rst;
always #10 sys_clk = ~sys_clk;


initial begin
    sys_clk <= 1'b0;
    sys_rst <= 1'b0;
    #50
    sys_rst <= 1'b1;
end
ram u_ram(
    .sys_clk(sys_clk),
    .sys_rst(sys_rst)
);

endmodule