仿真通过
阳光少年
8 months ago
parent
720eabcfe4
commit
77caedf906
@ -0,0 +1,97 @@
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#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
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:ivl_version "12.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 9;
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
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S_0x7f9736404160 .scope module, "tb_dt" "tb_dt" 2 2;
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.timescale -9 -9;
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v0x7f9736404340_0 .var "CNT", 5 0;
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v0x7f97365140b0_0 .var "data", 7 0;
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v0x7f9736514160_0 .var "sys_clk", 0 0;
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v0x7f9736514210_0 .var "sys_rst", 0 0;
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E_0x7f97364042e0/0 .event negedge, v0x7f9736514210_0;
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E_0x7f97364042e0/1 .event posedge, v0x7f9736514160_0;
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E_0x7f97364042e0 .event/or E_0x7f97364042e0/0, E_0x7f97364042e0/1;
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.scope S_0x7f9736404160;
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T_0 ;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7f9736514160_0, 0;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7f9736514210_0, 0;
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%delay 200, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x7f9736514210_0, 0;
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%end;
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.thread T_0;
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.scope S_0x7f9736404160;
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T_1 ;
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%delay 10, 0;
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%load/vec4 v0x7f9736514160_0;
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%inv;
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%store/vec4 v0x7f9736514160_0, 0, 1;
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%jmp T_1;
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.thread T_1;
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.scope S_0x7f9736404160;
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T_2 ;
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%wait E_0x7f97364042e0;
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%load/vec4 v0x7f9736514210_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_2.0, 4;
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%pushi/vec4 0, 0, 6;
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%assign/vec4 v0x7f9736404340_0, 0;
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%jmp T_2.1;
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T_2.0 ;
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%load/vec4 v0x7f9736404340_0;
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%cmpi/u 24, 0, 6;
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%jmp/0xz T_2.2, 5;
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%load/vec4 v0x7f9736404340_0;
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%addi 1, 0, 6;
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%assign/vec4 v0x7f9736404340_0, 0;
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%jmp T_2.3;
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T_2.2 ;
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%pushi/vec4 0, 0, 6;
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%assign/vec4 v0x7f9736404340_0, 0;
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T_2.3 ;
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T_2.1 ;
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%jmp T_2;
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.thread T_2;
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.scope S_0x7f9736404160;
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T_3 ;
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%wait E_0x7f97364042e0;
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%load/vec4 v0x7f9736514210_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_3.0, 4;
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%pushi/vec4 128, 0, 8;
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%assign/vec4 v0x7f97365140b0_0, 0;
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%jmp T_3.1;
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T_3.0 ;
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%load/vec4 v0x7f9736404340_0;
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%cmpi/e 24, 0, 6;
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%jmp/0xz T_3.2, 4;
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%load/vec4 v0x7f97365140b0_0;
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%parti/s 4, 0, 2;
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%addi 1, 0, 4;
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%ix/load 4, 0, 0;
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%ix/load 5, 0, 0;
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%flag_set/imm 4, 0;
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%assign/vec4/off/d v0x7f97365140b0_0, 4, 5;
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%load/vec4 v0x7f97365140b0_0;
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%parti/s 2, 5, 4;
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%addi 1, 0, 2;
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%ix/load 4, 5, 0;
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%ix/load 5, 0, 0;
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%flag_set/imm 4, 0;
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%assign/vec4/off/d v0x7f97365140b0_0, 4, 5;
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T_3.2 ;
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T_3.1 ;
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%jmp T_3;
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.thread T_3;
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# The file index is used to find the file name in the following table.
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:file_names 3;
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"N/A";
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"<interactive>";
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"tb_dt.v";
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@ -0,0 +1,90 @@
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`timescale 1ns/1ns
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module tb_lm();
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reg k_1;
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reg k_2;
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reg flag; // 状态改变周期 现在500ns改变一次状态
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reg sys_clk;
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reg sys_rst;
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always #10 sys_clk = ~sys_clk;
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initial begin
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sys_clk <= 1'b0;
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sys_rst <= 1'b0;
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#200
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sys_rst <= 1'b1;
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{k_2, k_1} <= 2'b10;
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#4000
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{k_2, k_1} <= 2'b01;
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#4000
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{k_2, k_1} <= 2'b00;
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end
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reg [5:0] CNT;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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CNT <= 5'd0;
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end
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else if (CNT < (5'd25 - 5'd1)) begin
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CNT <= CNT + 5'd1;
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end
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else begin
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CNT <= 5'b0;
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end
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end
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reg [7:0]x;
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reg [7:0]y;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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k_1 <= 1'b0;
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k_2 <= 1'b0;
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x <= 8'b00000000;
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y <= 8'b11111111; // 所有的都显示算了
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end
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else if ({k_2, k_1} == 2'b10) begin
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case (flag)
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1'b0: x <= 8'b1010_1010;
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1'b1: x <= 8'b0101_0101;
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endcase
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end
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else if ({k_2, k_1} == 2'b01) begin
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case (flag)
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1'b0: x <= 8'b1111_0000;
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1'b1: x <= 8'b0000_1111;
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endcase
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end
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else begin
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x <= 8'b00000000;
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end
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end
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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flag <= 1'b0;
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end
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else if (CNT == (5'd25 - 5'd1)) begin
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flag <= !flag;
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end
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else begin
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end
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end
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lm u_lm(
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.x (x),
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.y (y)
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);
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endmodule
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@ -0,0 +1,167 @@
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#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
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:ivl_version "12.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 9;
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
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S_0x7fb95300a8d0 .scope module, "tb_lm" "tb_lm" 2 3;
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.timescale -9 -9;
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v0x7fb953008920_0 .var "CNT", 5 0;
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v0x7fb95301a6d0_0 .var "flag", 0 0;
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v0x7fb95301a770_0 .var "k_1", 0 0;
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v0x7fb95301a800_0 .var "k_2", 0 0;
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v0x7fb95301a8a0_0 .var "sys_clk", 0 0;
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v0x7fb95301a980_0 .var "sys_rst", 0 0;
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v0x7fb95301aa20_0 .var "x", 7 0;
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v0x7fb95301aad0_0 .var "y", 7 0;
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E_0x7fb9530086e0/0 .event negedge, v0x7fb95301a980_0;
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E_0x7fb9530086e0/1 .event posedge, v0x7fb95301a8a0_0;
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E_0x7fb9530086e0 .event/or E_0x7fb9530086e0/0, E_0x7fb9530086e0/1;
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.scope S_0x7fb95300a8d0;
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T_0 ;
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%delay 10, 0;
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%load/vec4 v0x7fb95301a8a0_0;
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%inv;
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%store/vec4 v0x7fb95301a8a0_0, 0, 1;
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%jmp T_0;
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.thread T_0;
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.scope S_0x7fb95300a8d0;
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T_1 ;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fb95301a8a0_0, 0;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fb95301a980_0, 0;
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%delay 200, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x7fb95301a980_0, 0;
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%end;
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.thread T_1;
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.scope S_0x7fb95300a8d0;
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T_2 ;
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%wait E_0x7fb9530086e0;
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%load/vec4 v0x7fb95301a980_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_2.0, 4;
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%pushi/vec4 0, 0, 6;
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%assign/vec4 v0x7fb953008920_0, 0;
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%jmp T_2.1;
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T_2.0 ;
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%load/vec4 v0x7fb953008920_0;
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%cmpi/u 24, 0, 6;
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%jmp/0xz T_2.2, 5;
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%load/vec4 v0x7fb953008920_0;
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%addi 1, 0, 6;
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%assign/vec4 v0x7fb953008920_0, 0;
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%jmp T_2.3;
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T_2.2 ;
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%pushi/vec4 0, 0, 6;
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%assign/vec4 v0x7fb953008920_0, 0;
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T_2.3 ;
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T_2.1 ;
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%jmp T_2;
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.thread T_2;
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.scope S_0x7fb95300a8d0;
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T_3 ;
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%wait E_0x7fb9530086e0;
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%load/vec4 v0x7fb95301a980_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_3.0, 4;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fb95301a770_0, 0;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fb95301a800_0, 0;
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%pushi/vec4 0, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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%pushi/vec4 255, 0, 8;
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%assign/vec4 v0x7fb95301aad0_0, 0;
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%jmp T_3.1;
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T_3.0 ;
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%load/vec4 v0x7fb95301a800_0;
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%load/vec4 v0x7fb95301a770_0;
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%concat/vec4; draw_concat_vec4
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%cmpi/e 2, 0, 2;
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%jmp/0xz T_3.2, 4;
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%load/vec4 v0x7fb95301a6d0_0;
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%dup/vec4;
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%pushi/vec4 0, 0, 1;
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%cmp/u;
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%jmp/1 T_3.4, 6;
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%dup/vec4;
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%pushi/vec4 1, 0, 1;
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%cmp/u;
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%jmp/1 T_3.5, 6;
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%jmp T_3.6;
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T_3.4 ;
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%pushi/vec4 170, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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%jmp T_3.6;
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T_3.5 ;
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%pushi/vec4 85, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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%jmp T_3.6;
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T_3.6 ;
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%pop/vec4 1;
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%jmp T_3.3;
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T_3.2 ;
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%load/vec4 v0x7fb95301a800_0;
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%load/vec4 v0x7fb95301a770_0;
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%concat/vec4; draw_concat_vec4
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%cmpi/e 1, 0, 2;
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%jmp/0xz T_3.7, 4;
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%load/vec4 v0x7fb95301a6d0_0;
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%dup/vec4;
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%pushi/vec4 0, 0, 1;
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%cmp/u;
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%jmp/1 T_3.9, 6;
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%dup/vec4;
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%pushi/vec4 1, 0, 1;
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%cmp/u;
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%jmp/1 T_3.10, 6;
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%jmp T_3.11;
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T_3.9 ;
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%pushi/vec4 240, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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%jmp T_3.11;
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T_3.10 ;
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%pushi/vec4 15, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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%jmp T_3.11;
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T_3.11 ;
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%pop/vec4 1;
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%jmp T_3.8;
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T_3.7 ;
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%pushi/vec4 0, 0, 8;
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%assign/vec4 v0x7fb95301aa20_0, 0;
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T_3.8 ;
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T_3.3 ;
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T_3.1 ;
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%jmp T_3;
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.thread T_3;
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.scope S_0x7fb95300a8d0;
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T_4 ;
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%wait E_0x7fb9530086e0;
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%load/vec4 v0x7fb95301a980_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_4.0, 4;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x7fb95301a6d0_0, 0;
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%jmp T_4.1;
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T_4.0 ;
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%load/vec4 v0x7fb953008920_0;
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%cmpi/e 24, 0, 6;
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%jmp/0xz T_4.2, 4;
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%load/vec4 v0x7fb95301a6d0_0;
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%nor/r;
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%assign/vec4 v0x7fb95301a6d0_0, 0;
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T_4.2 ;
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T_4.1 ;
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%jmp T_4;
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.thread T_4;
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# The file index is used to find the file name in the following table.
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:file_names 3;
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"N/A";
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"<interactive>";
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"tb_lm.v";
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Reference in New Issue