Recoded pcileech connector by using the leechcore library. Some test-implementations for read/write already exist; very WIP
ko1N
4 years ago
parent
21315c77ec
commit
27a970aad2
@ -1,2 +1,2 @@
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[target.'cfg(unix)']
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runner = "sudo"
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runner = "sudo -E"
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@ -0,0 +1,3 @@
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[submodule "leechcore-sys/src/leechcore"]
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path = leechcore-sys/src/leechcore
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url = https://github.com/ufrisk/LeechCore
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@ -1,34 +1,9 @@
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[package]
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name = "memflow-pcileech"
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version = "0.1.0"
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authors = ["ko1N <ko1N1337@gmail.com>"]
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edition = "2018"
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description = "pcileech fpga connector for the memflow physical memory introspection framework"
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homepage = "https://github.com/memflow/memflow-pcileech"
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repository = "https://github.com/memflow/memflow-pcileech"
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readme = "README.md"
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[lib]
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crate-type = ["lib", "cdylib"]
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[dependencies]
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memflow = { version = "0.1", features = ["inventory"] }
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memflow-derive = "0.1"
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log = { version = "0.4.8", default-features = false }
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rusb = "0.6.0"
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dataview = "0.1"
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pretty-hex = "0.1"
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c2rust-bitfields = "0.3.0"
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libc = "0.2"
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[dev-dependencies]
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clap = "2.33.0"
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simple_logger = "1.0.1"
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[features]
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default = []
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plugin = []
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[[example]]
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name = "read_pcileech"
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path = "examples/read_pcileech.rs"
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[workspace]
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members = [
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"leechcore-sys",
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"memflow-pcileech",
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]
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default-members = [
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"leechcore-sys",
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"memflow-pcileech",
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]
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@ -1,21 +1,674 @@
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MIT License
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Copyright (c) 2020 ko1N <ko1N1337@gmail.com>
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Permission is hereby granted, free of charge, to any person obtaining a copy
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|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
{one line to give the program's name and a brief idea of what it does.}
|
||||
Copyright (C) {year} {name of author}
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
{project} Copyright (C) {year} {fullname}
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
|
||||
@ -1,168 +0,0 @@
|
||||
// Example program
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
#include <cstdint>
|
||||
|
||||
#define WORD uint16_t
|
||||
#define DWORD uint32_t
|
||||
#define BYTE uint8_t
|
||||
#define PBYTE uint8_t*
|
||||
#define TRUE 1
|
||||
#define BOOL int
|
||||
#define QWORD uint64_t
|
||||
#define FALSE 0
|
||||
#define PDWORD DWORD*
|
||||
|
||||
#define ENDIAN_SWAP_DWORD(x) (x = (x << 24) | ((x >> 8) & 0xff00) | ((x << 8) & 0xff0000) | (x >> 24))
|
||||
|
||||
#define TLP_MRd32 0x00
|
||||
#define TLP_MRd64 0x20
|
||||
#define TLP_MRdLk32 0x01
|
||||
#define TLP_MRdLk64 0x21
|
||||
#define TLP_MWr32 0x40
|
||||
#define TLP_MWr64 0x60
|
||||
#define TLP_IORd 0x02
|
||||
#define TLP_IOWr 0x42
|
||||
#define TLP_CfgRd0 0x04
|
||||
#define TLP_CfgRd1 0x05
|
||||
#define TLP_CfgWr0 0x44
|
||||
#define TLP_CfgWr1 0x45
|
||||
#define TLP_Cpl 0x0A
|
||||
#define TLP_CplD 0x4A
|
||||
#define TLP_CplLk 0x0B
|
||||
#define TLP_CplDLk 0x4B
|
||||
|
||||
#define MAX_SIZE_TX 0x3f0
|
||||
|
||||
typedef struct tdTLP_HDR {
|
||||
WORD Length : 10;
|
||||
WORD _AT : 2;
|
||||
WORD _Attr : 2;
|
||||
WORD _EP : 1;
|
||||
WORD _TD : 1;
|
||||
BYTE _R1 : 4;
|
||||
BYTE _TC : 3;
|
||||
BYTE _R2 : 1;
|
||||
BYTE TypeFmt;
|
||||
} TLP_HDR, *PTLP_HDR;
|
||||
|
||||
typedef struct tdTLP_HDR_MRdWr32 {
|
||||
TLP_HDR h;
|
||||
BYTE FirstBE : 4;
|
||||
BYTE LastBE : 4;
|
||||
BYTE Tag;
|
||||
WORD RequesterID;
|
||||
DWORD Address;
|
||||
} TLP_HDR_MRdWr32, *PTLP_HDR_MRdWr32;
|
||||
|
||||
typedef struct tdTLP_HDR_MRdWr64 {
|
||||
TLP_HDR h;
|
||||
BYTE FirstBE : 4;
|
||||
BYTE LastBE : 4;
|
||||
BYTE Tag;
|
||||
WORD RequesterID;
|
||||
DWORD AddressHigh;
|
||||
DWORD AddressLow;
|
||||
} TLP_HDR_MRdWr64, *PTLP_HDR_MRdWr64;
|
||||
|
||||
int pfnFT_WritePipe(PBYTE pb, DWORD cb) {
|
||||
printf("writepipe: %d bytes\n", cb);
|
||||
|
||||
for (int i = 0; i < cb; i++) {
|
||||
printf("%d, ", (int)pb[i]);
|
||||
}
|
||||
|
||||
printf("\n\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
BOOL DeviceFPGA_TxTlp(PBYTE pbTlp, DWORD cbTlp, BOOL fRdKeepalive, BOOL fFlush)
|
||||
{
|
||||
PBYTE txbuf_pb = (PBYTE)malloc(0x1000 * 32);
|
||||
DWORD txbuf_cb = 0;
|
||||
|
||||
DWORD status;
|
||||
PBYTE pbTx;
|
||||
QWORD i;
|
||||
DWORD cbTx, cbTxed = 0;
|
||||
if(cbTlp & 0x3) { return FALSE; }
|
||||
if(cbTlp > 4 * 4 + 128) { return FALSE; }
|
||||
if(cbTlp && (txbuf_cb + (cbTlp << 1) + (fFlush ? 8 : 0) >= MAX_SIZE_TX)) {
|
||||
if(!DeviceFPGA_TxTlp(NULL, 0, FALSE, TRUE)) { return FALSE; }
|
||||
}
|
||||
//if(ctxLC->fPrintf[LC_PRINTF_VVV]) {
|
||||
// TLP_Print(ctxLC, pbTlp, cbTlp, TRUE);
|
||||
//}
|
||||
// prepare transmit buffer
|
||||
pbTx = txbuf_pb + txbuf_cb;
|
||||
cbTx = 2 * cbTlp;
|
||||
for(i = 0; i < cbTlp; i += 4) {
|
||||
*(PDWORD)(pbTx + (i << 1)) = *(PDWORD)(pbTlp + i);
|
||||
*(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77000000; // TX TLP
|
||||
}
|
||||
if(cbTlp) {
|
||||
*(PDWORD)(pbTx + ((i << 1) - 4)) = 0x77040000; // TX TLP VALID LAST
|
||||
}
|
||||
if(fRdKeepalive) {
|
||||
cbTx += 8;
|
||||
*(PDWORD)(pbTx + (i << 1)) = 0xffeeddcc;
|
||||
*(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77020000; // LOOPBACK TX
|
||||
}
|
||||
txbuf_cb += cbTx;
|
||||
// transmit
|
||||
if((txbuf_cb >= MAX_SIZE_TX) || (fFlush && txbuf_cb)) {
|
||||
status = pfnFT_WritePipe(txbuf_pb, txbuf_cb);
|
||||
if(status == 0x20) {
|
||||
//DeviceFPGA_ReInitializeFTDI(ctx); // try recovery if possible.
|
||||
status = pfnFT_WritePipe(txbuf_pb, txbuf_cb);
|
||||
}
|
||||
txbuf_cb = 0;
|
||||
//usleep(ctx->perf.DELAY_WRITE);
|
||||
return (0 == status);
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
DWORD tx[4] = { 0 };
|
||||
PBYTE txb = (PBYTE)tx;
|
||||
PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx;
|
||||
PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx;
|
||||
|
||||
printf("stuff: 0x%x\n", (WORD)(0x123 >> 2));
|
||||
/*
|
||||
hdrRd32->h.TypeFmt = TLP_MRd64;
|
||||
hdrRd32->h.Length = (WORD)(0x123 >> 2);
|
||||
*/
|
||||
hdrRd32->h.TypeFmt = TLP_MRd32;
|
||||
hdrRd32->h.Length = (WORD)(0x123 >> 2);
|
||||
hdrRd32->RequesterID = 17;
|
||||
hdrRd32->Tag = 0x80;
|
||||
hdrRd32->FirstBE = 0xf;
|
||||
hdrRd32->LastBE = 0xf;
|
||||
|
||||
hdrRd32->Address = (DWORD)(0x6000);
|
||||
//uint64_t addr = 0x100000000 + 0x6000;
|
||||
//hdrRd64->AddressHigh = (DWORD)(addr >> 32);
|
||||
//hdrRd64->AddressLow = (DWORD)(addr);
|
||||
|
||||
//printf("sizeof 32: 0x%x\n", sizeof(TLP_HDR_MRdWr32));
|
||||
//printf("sizeof 64: 0x%x\n", sizeof(TLP_HDR_MRdWr64));
|
||||
|
||||
printf("tlp:\n");
|
||||
for (int i = 0; i < 16; i++) {
|
||||
printf("%d ", (int)txb[i]);
|
||||
//printf("%X ", tx[i]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
for(int j = 0; j < 4; j++) {
|
||||
ENDIAN_SWAP_DWORD(tx[j]);
|
||||
}
|
||||
|
||||
DeviceFPGA_TxTlp((PBYTE)tx, /*is32 ? 12 : 16*/ 12, FALSE, TRUE);
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
use log::Level;
|
||||
|
||||
use memflow::connector::ConnectorArgs;
|
||||
use memflow_pcileech::{create_connector, PcieGen};
|
||||
|
||||
fn main() {
|
||||
simple_logger::init_with_level(Level::Trace).unwrap();
|
||||
let mut conn = create_connector(&ConnectorArgs::new()).unwrap();
|
||||
conn.set_pcie_gen(PcieGen::Gen2).unwrap();
|
||||
|
||||
// TODO: put this + more in a conn print trait ->
|
||||
println!(
|
||||
"pcie device opened with link width {} and pcie gen {:?}",
|
||||
conn.pcie_link_width(),
|
||||
conn.pcie_gen()
|
||||
);
|
||||
|
||||
conn.test_read().unwrap();
|
||||
}
|
||||
@ -0,0 +1,19 @@
|
||||
#!/bin/bash
|
||||
|
||||
cargo build --release --all-features
|
||||
|
||||
# install connector to system dir
|
||||
if [ ! -z "$1" ] && [ $1 = "--system" ]; then
|
||||
echo "installing connector system-wide in /usr/lib/memflow"
|
||||
if [[ ! -d /usr/lib/memflow ]]; then
|
||||
sudo mkdir /usr/lib/memflow
|
||||
fi
|
||||
sudo cp target/release/libmemflow_pcileech.so /usr/lib/memflow
|
||||
fi
|
||||
|
||||
# install connector in user dir
|
||||
echo "installing connector for user in ~/.local/lib/memflow"
|
||||
if [[ ! -d ~/.local/lib/memflow ]]; then
|
||||
mkdir -p ~/.local/lib/memflow
|
||||
fi
|
||||
cp target/release/libmemflow_pcileech.so ~/.local/lib/memflow
|
||||
@ -0,0 +1,14 @@
|
||||
[package]
|
||||
name = "leechcore-sys"
|
||||
version = "0.1.0"
|
||||
authors = ["ko1N <ko1N1337@gmail.com>"]
|
||||
edition = "2018"
|
||||
readme = "../README.md"
|
||||
license-file = "../LICENSE"
|
||||
|
||||
links = "leechcore"
|
||||
|
||||
[build-dependencies]
|
||||
cc = "1.0.62"
|
||||
bindgen = "0.55"
|
||||
pkg-config = "0.3"
|
||||
@ -0,0 +1,82 @@
|
||||
extern crate bindgen;
|
||||
extern crate cc;
|
||||
extern crate pkg_config;
|
||||
|
||||
use std::env;
|
||||
use std::path::PathBuf;
|
||||
use std::process::Command;
|
||||
|
||||
#[cfg(target_os = "windows")]
|
||||
fn os_define() -> &'static str {
|
||||
"_WIN32"
|
||||
}
|
||||
|
||||
#[cfg(target_os = "linux")]
|
||||
fn os_define() -> &'static str {
|
||||
"LINUX"
|
||||
}
|
||||
|
||||
fn main() -> () {
|
||||
//let target = env::var("TARGET").unwrap();
|
||||
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
|
||||
|
||||
let objs = vec![
|
||||
"oscompatibility.c",
|
||||
"leechcore.c",
|
||||
"util.c",
|
||||
"memmap.c",
|
||||
"device_file.c",
|
||||
"device_fpga.c",
|
||||
"device_pmem.c",
|
||||
"device_tmd.c",
|
||||
"device_usb3380.c",
|
||||
"leechrpcclient.c",
|
||||
];
|
||||
|
||||
pkg_config::probe_library("libusb-1.0")
|
||||
.unwrap_or_else(|err| panic!("Failed to find libusb-1.0 via pkg-config: {:?}", err));
|
||||
|
||||
// TODO: windows
|
||||
// TODO: pkg_config ?
|
||||
let libusb_flags = Command::new("pkg-config")
|
||||
.args(&["libusb-1.0", "--libs", "--cflags"])
|
||||
.output()
|
||||
.unwrap_or_else(|err| panic!("Failed to find libusb-1.0 via pkg-config: {:?}", err));
|
||||
|
||||
let mut cfg = cc::Build::new();
|
||||
cfg.cpp(false)
|
||||
.files(
|
||||
objs.iter()
|
||||
.map(|o| "src/leechcore/leechcore/".to_string() + o)
|
||||
.collect::<Vec<_>>(),
|
||||
)
|
||||
.flag(&format!("-D{}", os_define()))
|
||||
.flag("-fPIC")
|
||||
.flag("-fvisibility=hidden")
|
||||
.flag("-pthread")
|
||||
.flag("-g")
|
||||
.flag("-ldl");
|
||||
|
||||
for flag in String::from_utf8_lossy(&libusb_flags.stdout)
|
||||
.trim()
|
||||
.split(" ")
|
||||
{
|
||||
cfg.flag(flag);
|
||||
}
|
||||
|
||||
cfg.compile("libleechcore.a");
|
||||
|
||||
// generate bindings
|
||||
let bindings = bindgen::builder()
|
||||
.clang_arg(format!("-D{}", os_define()))
|
||||
.header("./src/leechcore/leechcore/leechcore.h")
|
||||
.generate()
|
||||
.unwrap_or_else(|err| panic!("Failed to generate bindings: {:?}", err));
|
||||
|
||||
let bindings_path = out_dir.join("leechcore.rs");
|
||||
bindings
|
||||
.write_to_file(&bindings_path)
|
||||
.unwrap_or_else(|_| panic!("Failed to write {}", bindings_path.display()));
|
||||
|
||||
println!("cargo:rustc-link-lib=static=leechcore");
|
||||
}
|
||||
@ -0,0 +1 @@
|
||||
Subproject commit 9a744a313a023bde5b8e710597f3690a27561906
|
||||
@ -0,0 +1,8 @@
|
||||
#![allow(non_snake_case)]
|
||||
#![allow(non_camel_case_types)]
|
||||
#![allow(non_upper_case_globals)]
|
||||
#![allow(clippy::useless_transmute)]
|
||||
#![allow(clippy::cognitive_complexity)]
|
||||
#![allow(clippy::missing_safety_doc)]
|
||||
|
||||
include!(concat!(env!("OUT_DIR"), "/leechcore.rs"));
|
||||
@ -0,0 +1,40 @@
|
||||
[package]
|
||||
name = "memflow-pcileech"
|
||||
version = "0.1.0"
|
||||
authors = ["ko1N <ko1N1337@gmail.com>"]
|
||||
edition = "2018"
|
||||
description = "qemu procfs connector for leechcore/pcileech"
|
||||
documentation = "https://docs.rs/memflow-pcileech"
|
||||
readme = "../README.md"
|
||||
homepage = "https://memflow.github.io"
|
||||
repository = "https://github.com/memflow/memflow-pcileech"
|
||||
license-file = "../LICENSE"
|
||||
keywords = [ "memflow", "introspection", "memory" ]
|
||||
categories = [ "api-bindings", "memory-management", "os" ]
|
||||
|
||||
[lib]
|
||||
crate-type = ["lib", "cdylib"]
|
||||
|
||||
[dependencies]
|
||||
memflow = { version = "0.1", features = ["inventory"] }
|
||||
memflow-derive = { version = "0.1" }
|
||||
log = { version = "0.4", default-features = false }
|
||||
leechcore-sys = { path = "../leechcore-sys" }
|
||||
|
||||
# test
|
||||
libc = "0.2"
|
||||
|
||||
[dev-dependencies]
|
||||
clap = "2.33"
|
||||
simple_logger = "1.0"
|
||||
|
||||
[profile.release]
|
||||
lto = true
|
||||
|
||||
[features]
|
||||
default = []
|
||||
inventory = []
|
||||
|
||||
[[example]]
|
||||
name = "read_phys"
|
||||
path = "examples/read_phys.rs"
|
||||
@ -0,0 +1,48 @@
|
||||
use std::time::Instant;
|
||||
|
||||
use log::{info, Level};
|
||||
|
||||
use memflow::*;
|
||||
|
||||
fn main() {
|
||||
simple_logger::init_with_level(Level::Debug).unwrap();
|
||||
|
||||
// TODO: parse command-line args
|
||||
/*
|
||||
let mut conn = match memflow_pcileech::create_connector(
|
||||
&ConnectorArgs::parse("name=win10,type=kvm").unwrap(),
|
||||
) {
|
||||
Ok(br) => br,
|
||||
Err(e) => {
|
||||
info!("couldn't open memory read context: {:?}", e);
|
||||
return;
|
||||
}
|
||||
};
|
||||
*/
|
||||
let mut conn = memflow_pcileech::PciLeech::new("FPGA").unwrap();
|
||||
info!("conn: {:?}", conn);
|
||||
|
||||
let mut mem = vec![0; 8];
|
||||
conn.phys_read_raw_into(Address::from(0x1000).into(), &mut mem)
|
||||
.unwrap();
|
||||
info!("Received memory: {:?}", mem);
|
||||
|
||||
/*
|
||||
let start = Instant::now();
|
||||
let mut counter = 0;
|
||||
loop {
|
||||
let mut buf = vec![0; 0x1000];
|
||||
conn.phys_read_raw_into(Address::from(0x1000).into(), &mut buf)
|
||||
.unwrap();
|
||||
|
||||
counter += 1;
|
||||
if (counter % 10000) == 0 {
|
||||
let elapsed = start.elapsed().as_millis() as f64;
|
||||
if elapsed > 0.0 {
|
||||
info!("{} reads/sec", (f64::from(counter)) / elapsed * 1000.0);
|
||||
info!("{} ms/read", elapsed / (f64::from(counter)));
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
}
|
||||
@ -0,0 +1,170 @@
|
||||
// https://github.com/ufrisk/pcileech/blob/master/pcileech/device.c
|
||||
|
||||
use std::ffi::CString;
|
||||
use std::os::raw::c_char;
|
||||
|
||||
use libc::malloc;
|
||||
use log::{error, info, warn};
|
||||
|
||||
use memflow::*;
|
||||
use memflow_derive::connector;
|
||||
|
||||
use leechcore_sys::*;
|
||||
|
||||
fn build_lc_config(device: &str) -> LC_CONFIG {
|
||||
let cdevice = unsafe { &*(device.as_bytes() as *const [u8] as *const [i8]) };
|
||||
let mut adevice: [c_char; 260] = [0; 260];
|
||||
// adevice.clone_from_slice(unsafe { &*(cdevice.as_bytes_with_nul() as *const [u8] as *const [i8]) });
|
||||
adevice[..device.len().min(260)].copy_from_slice(&cdevice[..device.len().min(260)]);
|
||||
|
||||
let cfg = LC_CONFIG {
|
||||
dwVersion: LC_CONFIG_VERSION,
|
||||
dwPrintfVerbosity: LC_CONFIG_PRINTF_ENABLED | LC_CONFIG_PRINTF_V | LC_CONFIG_PRINTF_VV,
|
||||
szDevice: adevice,
|
||||
szRemote: [0; 260],
|
||||
pfn_printf_opt: None, // TODO: custom info() wrapper
|
||||
paMax: 0,
|
||||
fVolatile: 0,
|
||||
fWritable: 0,
|
||||
fRemote: 0,
|
||||
fRemoteDisableCompress: 0,
|
||||
szDeviceName: [0; 260],
|
||||
};
|
||||
|
||||
// TODO: copy device + remote
|
||||
|
||||
cfg
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct PciLeech {
|
||||
handle: HANDLE,
|
||||
}
|
||||
|
||||
// TODO:
|
||||
unsafe impl Send for PciLeech {}
|
||||
|
||||
// TODO: implement me
|
||||
impl Clone for PciLeech {
|
||||
fn clone(&self) -> Self {
|
||||
panic!("unable to clone pcileech connector");
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: proper drop + free impl -> LcMemFree(pLcErrorInfo);
|
||||
impl PciLeech {
|
||||
pub fn new(device: &str) -> Result<Self> {
|
||||
// open device
|
||||
let mut conf = build_lc_config(device);
|
||||
let err = std::ptr::null_mut::<PLC_CONFIG_ERRORINFO>();
|
||||
let handle = unsafe { LcCreateEx(&mut conf, err) };
|
||||
if handle.is_null() {
|
||||
// TODO: handle version error
|
||||
// TODO: handle special case of fUserInputRequest
|
||||
error!("leechcore error: {:?}", err);
|
||||
return Err(Error::Connector("unable to create leechcore context"));
|
||||
}
|
||||
|
||||
Ok(Self { handle })
|
||||
}
|
||||
}
|
||||
|
||||
impl PhysicalMemory for PciLeech {
|
||||
fn phys_read_raw_list(&mut self, data: &mut [PhysicalReadData]) -> Result<()> {
|
||||
// TODO: everything apart from 0x1000 byte buffers crashes...
|
||||
for read in data.iter_mut() {
|
||||
// TODO: ensure reading just 1 page...
|
||||
// TODO: handle page boundaries
|
||||
if read.1.len() < 0x1000 {
|
||||
let mut page = [0u8; 0x1000];
|
||||
let aligned = read.0.address().as_page_aligned(0x1000);
|
||||
unsafe {
|
||||
LcRead(
|
||||
self.handle,
|
||||
aligned.as_u64(),
|
||||
page.len() as u32,
|
||||
page.as_mut_ptr(),
|
||||
)
|
||||
};
|
||||
let offs = (read.0.as_u64() - aligned.as_u64()) as usize;
|
||||
read.1.copy_from_slice(&page[offs..offs + read.1.len()]);
|
||||
} else {
|
||||
// TODO: handle multiple pages at once
|
||||
// TODO: handle page alignment
|
||||
unsafe {
|
||||
LcRead(
|
||||
self.handle,
|
||||
read.0.as_u64(),
|
||||
read.1.len() as u32,
|
||||
read.1.as_mut_ptr(),
|
||||
)
|
||||
};
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> {
|
||||
// TODO: everything apart from 0x1000 byte buffers crashes...
|
||||
unsafe {
|
||||
for write in data.iter() {
|
||||
LcWrite(
|
||||
self.handle,
|
||||
write.0.as_u64(),
|
||||
write.1.len() as u32,
|
||||
write.1.as_ptr() as *mut u8,
|
||||
);
|
||||
|
||||
/*
|
||||
// TODO: ensure reading just 1 page...
|
||||
// TODO: handle page boundaries
|
||||
if write.1.len() < 0x1000 {
|
||||
let mut page = [0u8; 0x1000];
|
||||
let aligned = write.0.address().as_page_aligned(0x1000);
|
||||
unsafe {
|
||||
LcRead(
|
||||
self.handle,
|
||||
aligned.as_u64(),
|
||||
page.len() as u32,
|
||||
page.as_mut_ptr(),
|
||||
)
|
||||
};
|
||||
let offs = (read.0.as_u64() - aligned.as_u64()) as usize;
|
||||
read.1.copy_from_slice(
|
||||
&page[offs..offs+read.1.len()],
|
||||
);
|
||||
} else {
|
||||
// TODO: handle multiple pages at once
|
||||
// TODO: handle page alignment
|
||||
unsafe {
|
||||
LcRead(
|
||||
self.handle,
|
||||
read.0.as_u64(),
|
||||
read.1.len() as u32,
|
||||
read.1.as_mut_ptr(),
|
||||
)
|
||||
};
|
||||
}
|
||||
*/
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn metadata(&self) -> PhysicalMemoryMetadata {
|
||||
PhysicalMemoryMetadata {
|
||||
size: size::gb(16), // TODO:
|
||||
readonly: false,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Creates a new PciLeech Connector instance.
|
||||
#[connector(name = "pcileech")]
|
||||
pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
|
||||
let device = args
|
||||
.get("device")
|
||||
.or_else(|| args.get_default())
|
||||
.ok_or(Error::Connector("argument 'device' missing"))?;
|
||||
PciLeech::new(device)
|
||||
}
|
||||
@ -1,800 +0,0 @@
|
||||
// TODO: unpub?
|
||||
pub mod tlps;
|
||||
use tlps::*;
|
||||
|
||||
use crate::ft60x::*;
|
||||
|
||||
use core::mem::MaybeUninit;
|
||||
use core::time::Duration;
|
||||
|
||||
use log::{info, trace, warn};
|
||||
|
||||
use memflow::{
|
||||
error::{Error, Result},
|
||||
size,
|
||||
};
|
||||
|
||||
use c2rust_bitfields::*;
|
||||
use dataview::Pod;
|
||||
use pretty_hex::*;
|
||||
|
||||
pub const FPGA_CONFIG_CORE: u16 = 0x0003;
|
||||
pub const FPGA_CONFIG_PCIE: u16 = 0x0001;
|
||||
pub const FPGA_CONFIG_SPACE_READONLY: u16 = 0x0000;
|
||||
pub const FPGA_CONFIG_SPACE_READWRITE: u16 = 0x8000;
|
||||
|
||||
// TODO: remove unused
|
||||
#[allow(unused)]
|
||||
pub struct PhyConfig {
|
||||
magic: u8, // 8 bit
|
||||
tp_cfg: u8, // 4 bit
|
||||
tp: u8, // 4 bit
|
||||
pub wr: PhyConfigWr, // 16 bits
|
||||
pub rd: PhyConfigRd, // 32 bits
|
||||
}
|
||||
|
||||
#[repr(C, align(1))]
|
||||
#[derive(BitfieldStruct, Pod)]
|
||||
pub struct PhyConfigWr {
|
||||
#[bitfield(name = "pl_directed_link_auton", ty = "libc::uint8_t", bits = "0..=0")]
|
||||
#[bitfield(name = "pl_directed_link_change", ty = "libc::uint8_t", bits = "1..=2")]
|
||||
#[bitfield(name = "pl_directed_link_speed", ty = "libc::uint8_t", bits = "3..=3")]
|
||||
#[bitfield(name = "pl_directed_link_width", ty = "libc::uint8_t", bits = "4..=5")]
|
||||
#[bitfield(name = "pl_upstream_prefer_deemph", ty = "libc::uint8_t", bits = "6..=6")]
|
||||
#[bitfield(name = "pl_transmit_hot_rst", ty = "libc::uint8_t", bits = "7..=7")]
|
||||
#[bitfield(name = "pl_downstream_deemph_source", ty = "libc::uint8_t", bits = "8..=8")]
|
||||
buffer: [u8; 2],
|
||||
}
|
||||
const _: [(); core::mem::size_of::<PhyConfigWr>()] = [(); 2];
|
||||
|
||||
#[repr(C, align(1))]
|
||||
#[derive(BitfieldStruct, Pod)]
|
||||
pub struct PhyConfigRd {
|
||||
#[bitfield(name = "pl_ltssm_state", ty = "libc::uint8_t", bits = "0..=5")]
|
||||
#[bitfield(name = "pl_rx_pm_state", ty = "libc::uint8_t", bits = "6..=7")]
|
||||
#[bitfield(name = "pl_tx_pm_state", ty = "libc::uint8_t", bits = "8..=10")]
|
||||
#[bitfield(name = "pl_initial_link_width", ty = "libc::uint8_t", bits = "11..=13")]
|
||||
#[bitfield(name = "pl_lane_reversal_mode", ty = "libc::uint8_t", bits = "14..=15")]
|
||||
#[bitfield(name = "pl_sel_lnk_width", ty = "libc::uint8_t", bits = "16..=17")]
|
||||
#[bitfield(name = "pl_phy_lnk_up", ty = "libc::uint8_t", bits = "18..=18")]
|
||||
#[bitfield(name = "pl_link_gen2_cap", ty = "libc::uint8_t", bits = "19..=19")]
|
||||
#[bitfield(name = "pl_link_partner_gen2_supported", ty = "libc::uint8_t", bits = "20..=20")]
|
||||
#[bitfield(name = "pl_link_upcfg_cap", ty = "libc::uint8_t", bits = "21..=21")]
|
||||
#[bitfield(name = "pl_sel_lnk_rate", ty = "libc::uint8_t", bits = "22..=22")]
|
||||
#[bitfield(name = "pl_directed_change_done", ty = "libc::uint8_t", bits = "23..=23")]
|
||||
#[bitfield(name = "pl_received_hot_rst", ty = "libc::uint8_t", bits = "24..=24")]
|
||||
buffer: [u8; 4],
|
||||
}
|
||||
const _: [(); core::mem::size_of::<PhyConfigRd>()] = [(); 4];
|
||||
|
||||
pub struct Device {
|
||||
ft60: FT60x,
|
||||
}
|
||||
|
||||
impl Device {
|
||||
pub fn new() -> Result<Self> {
|
||||
let mut ft60 = FT60x::new()?;
|
||||
ft60.abort_pipe(0x02)?;
|
||||
ft60.abort_pipe(0x82)?;
|
||||
|
||||
ft60.set_suspend_timeout(Duration::new(0, 0))?;
|
||||
|
||||
// check chip configuration
|
||||
let mut conf = ft60.config()?;
|
||||
info!(
|
||||
"ft60x config: fifo_mode={} channel_config={} optional_feature={}",
|
||||
conf.fifo_mode, conf.channel_config, conf.optional_feature_support
|
||||
);
|
||||
|
||||
if conf.fifo_mode != FifoMode::Mode245 as i8
|
||||
|| conf.channel_config != ChannelConfig::Config1 as i8
|
||||
|| conf.optional_feature_support != OptionalFeatureSupport::DisableAll as i16
|
||||
{
|
||||
warn!("bad ft60x config, reconfiguring chip");
|
||||
|
||||
conf.fifo_mode = FifoMode::Mode245 as i8;
|
||||
conf.channel_config = ChannelConfig::Config1 as i8;
|
||||
conf.optional_feature_support = OptionalFeatureSupport::DisableAll as i16;
|
||||
|
||||
ft60.set_config(&conf)?;
|
||||
} else {
|
||||
info!("ft60x config is valid");
|
||||
}
|
||||
|
||||
Ok(Self { ft60 })
|
||||
}
|
||||
|
||||
/// Restarts the PCIE device
|
||||
fn reset_core(&mut self) -> Result<()> {
|
||||
let reset_code: [u8; 2] = [0x00, 0x80];
|
||||
self.write_config_ex_raw(
|
||||
0x0002,
|
||||
reset_code,
|
||||
reset_code,
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE,
|
||||
)?;
|
||||
std::thread::sleep(Duration::from_millis(1000));
|
||||
self.ft60 = FT60x::new()?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Clears the pipe before starting any new read attempts
|
||||
pub fn clear_pipe(&mut self) -> Result<()> {
|
||||
let dummy = [
|
||||
// dword->qword resynch v4.5+
|
||||
0x66, 0x66, 0x55, 0x55, 0x66, 0x66, 0x55, 0x55, 0x66, 0x66, 0x55, 0x55, 0x66, 0x66,
|
||||
0x55, 0x55, // cmd msg: FPGA bitstream version (major.minor) v4
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x13, 0x77,
|
||||
// cmd msg: FPGA bitstream version (major) v3
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x77,
|
||||
];
|
||||
|
||||
//self.reset_core()?;
|
||||
|
||||
self.ft60.write_pipe(&dummy)?;
|
||||
|
||||
let mut buf = vec![0u8; size::mb(1)];
|
||||
if self.ft60.read_pipe(&mut buf[..0x1000])? >= 0x1000 {
|
||||
if self.ft60.read_pipe(&mut buf)? == buf.len() {
|
||||
self.reset_core()?;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read_version(&mut self) -> Result<(u8, u8)> {
|
||||
let version_major =
|
||||
self.read_config::<u8>(0x0008, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?;
|
||||
info!("version_major = {}", version_major);
|
||||
|
||||
let version_minor =
|
||||
self.read_config::<u8>(0x0009, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?;
|
||||
info!("version_minor={}", version_minor);
|
||||
|
||||
Ok((version_major, version_minor))
|
||||
}
|
||||
|
||||
pub fn read_devid(&mut self) -> Result<(u8, u16)> {
|
||||
let fpga_id =
|
||||
self.read_config::<u8>(0x000a, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?;
|
||||
info!("fpga_id={}", fpga_id);
|
||||
|
||||
let mut device_id = self
|
||||
.read_config::<u16>(0x0008, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)
|
||||
.unwrap_or_default();
|
||||
if device_id == 0 {
|
||||
info!("pci device_id is unset. checking pcie magic.");
|
||||
|
||||
let magic_pcie = self
|
||||
.read_config::<u16>(0x0000, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)
|
||||
.unwrap_or_default();
|
||||
info!("magic_pcie={:?}", magic_pcie);
|
||||
|
||||
if magic_pcie == 0x6745 {
|
||||
warn!("failed to get device_id. trying to recover via hot reset");
|
||||
self.hot_reset().ok();
|
||||
device_id = self
|
||||
.read_config::<u16>(0x0008, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)
|
||||
.unwrap_or_default();
|
||||
}
|
||||
}
|
||||
let device_id_le = device_id.to_be();
|
||||
info!("device_id={:?}", device_id_le);
|
||||
|
||||
// swap device_id bytes only on LE systems
|
||||
Ok((fpga_id, device_id_le))
|
||||
}
|
||||
|
||||
pub fn write_inactivity_timer(&mut self) -> Result<()> {
|
||||
let inactivity_timer = 0x000186a0u32; // set inactivity timer to 1ms (0x0186a0 * 100MHz) [only later activated on UDP bitstreams]
|
||||
self.write_config(
|
||||
0x0008,
|
||||
inactivity_timer,
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE,
|
||||
)
|
||||
}
|
||||
|
||||
pub fn hot_reset(&mut self) -> Result<()> {
|
||||
warn!("hot resetting the fpga");
|
||||
|
||||
let mut wr = self.get_phy_wr()?;
|
||||
wr.set_pl_transmit_hot_rst(1);
|
||||
self.set_phy_wr(&wr)?;
|
||||
|
||||
std::thread::sleep(Duration::from_millis(250)); // TODO: poll pl_ltssm_state + timeout with failure
|
||||
|
||||
wr.set_pl_transmit_hot_rst(0);
|
||||
self.set_phy_wr(&wr)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn get_phy(&mut self) -> Result<(PhyConfigWr, PhyConfigRd)> {
|
||||
Ok((self.get_phy_wr()?, self.get_phy_rd()?))
|
||||
}
|
||||
|
||||
pub fn get_phy_wr(&mut self) -> Result<PhyConfigWr> {
|
||||
let wr_raw =
|
||||
self.read_config::<u16>(0x0016, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)?;
|
||||
Ok(PhyConfigWr { buffer: u16::to_le_bytes(wr_raw) })
|
||||
}
|
||||
|
||||
pub fn set_phy_wr(&mut self, wr: &PhyConfigWr) -> Result<()> {
|
||||
self.write_config(0x0016, u16::from_le_bytes(wr.buffer), FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)
|
||||
}
|
||||
|
||||
pub fn get_phy_rd(&mut self) -> Result<PhyConfigRd> {
|
||||
let rd_raw =
|
||||
self.read_config::<u32>(0x000a, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)?;
|
||||
Ok(PhyConfigRd { buffer: u32::to_le_bytes(rd_raw) })
|
||||
}
|
||||
|
||||
/// Prints out all internal registers of the FPGA to `info!()`
|
||||
/// In detail this will request the core/pcie readonly and read/write registers
|
||||
/// and print them out via `info!()`. This is usually useful when debugging any
|
||||
/// issues with the hardware.
|
||||
pub fn print_registers(&mut self) -> Result<()> {
|
||||
info!(
|
||||
"core read-only registers: {:?}",
|
||||
self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?
|
||||
.hex_dump()
|
||||
);
|
||||
info!(
|
||||
"core read-write registers: {:?}",
|
||||
self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE)?
|
||||
.hex_dump()
|
||||
);
|
||||
info!(
|
||||
"pcie read-only registers: {:?}",
|
||||
self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)?
|
||||
.hex_dump()
|
||||
);
|
||||
info!(
|
||||
"core read-write registers: {:?}",
|
||||
self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)?
|
||||
.hex_dump()
|
||||
);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn get_register(&mut self, flags: u16) -> Result<Vec<u8>> {
|
||||
let size = self.read_config::<u16>(0x0004, flags)?;
|
||||
info!(
|
||||
"reading fpga device config register {:x} with a length of {:x} bytes.",
|
||||
flags, size
|
||||
);
|
||||
let mut buf = vec![0u8; size as usize];
|
||||
self.read_config_into_raw(0x0000, &mut buf[..], flags)?;
|
||||
Ok(buf)
|
||||
}
|
||||
|
||||
// TODO: implement more config dump options
|
||||
fn get_pcie_drp(&mut self) {
|
||||
let read_enable = [0x10, 0x00, 0x10, 0x00, 0x80, 0x02, 0x23, 0x77];
|
||||
let read_address = [0x00, 0x00, 0xff, 0xff, 0x80, 0x1c, 0x23, 0x77];
|
||||
let result_meta = [0x00, 0x00, 0x00, 0x00, 0x80, 0x1c, 0x13, 0x77];
|
||||
let result_data = [0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x13, 0x77];
|
||||
|
||||
// create read request
|
||||
for addr in (0..0x100).step_by(32) {
|
||||
for dw in (0..32).step_by(2) {}
|
||||
}
|
||||
|
||||
// interpret result
|
||||
}
|
||||
|
||||
// TODO: send_tlp_ ...
|
||||
/*pub fn send_tlp32(&mut self, tlp: u32, keep_alive: bool, flush: bool) -> Result<()> {
|
||||
self.send_tlp_raw(tlp.as_bytes(), keep_alive, flush)
|
||||
}
|
||||
|
||||
pub fn send_tlp64(&mut self, tlp: u64, keep_alive: bool, flush: bool) -> Result<()> {
|
||||
self.send_tlp_raw(tlp.as_bytes(), keep_alive, flush)
|
||||
}*/
|
||||
|
||||
// TODO: this is duplicated code (see config_parse_response)
|
||||
// https://github.com/ufrisk/LeechCore/blob/master/leechcore/device_fpga.c#L1603
|
||||
pub fn recv_tlps_64(&mut self, bytes: u32 /* maybe u16? */) -> Result<()> {
|
||||
let mut respbuf = vec![0u8; 0x4000]; // TEST
|
||||
self.ft60.read_pipe(&mut respbuf)?;
|
||||
|
||||
//let tlps = [0u8; 16+512]; // TLP_RX_MAX_SIZE
|
||||
//let tlp_num = 0;
|
||||
let mut tlps = Vec::new();
|
||||
|
||||
let view = respbuf.as_data_view();
|
||||
let mut skip = 0;
|
||||
for i in (0..respbuf.len()).step_by(32) {
|
||||
if i + skip >= respbuf.len() {
|
||||
break;
|
||||
}
|
||||
|
||||
while view.copy::<u32>(i + skip) == 0x55556666 {
|
||||
trace!("ftdi workaround detected, skipping 4 bytes");
|
||||
skip += 4;
|
||||
if i + skip + 32 > respbuf.len() {
|
||||
return Err(Error::Connector("out of range config read"));
|
||||
}
|
||||
}
|
||||
|
||||
let mut status = view.copy::<u32>(i + skip);
|
||||
if status & 0xf0000000 != 0xe0000000 {
|
||||
trace!("invalid status reply, skipping");
|
||||
continue;
|
||||
}
|
||||
|
||||
//trace!("parsing tlp data buffer");
|
||||
let mut tlp_offs = 0;
|
||||
for _ in 0..7 {
|
||||
if (status & 0x03) == 0 {
|
||||
// println!("pcie tlp received :)");
|
||||
tlps.push(view.copy::<u32>(i + skip + 4 + tlp_offs));
|
||||
// if(tlps.len() >= TLP_RX_MAX_SIZE / sizeof(DWORD)) { return; }
|
||||
}
|
||||
if (status & 0x07) == 4 {
|
||||
//println!("pcie tlp LAST received :)");
|
||||
// TODO: dispatch tlp buffer
|
||||
if tlps.len() >= 3 {
|
||||
println!("received {} tlps", tlps.len() << 2);
|
||||
// TODO: transmute tlps buffer to tlp header
|
||||
|
||||
} else {
|
||||
println!("received {} tlps - ERROR, Bad PCIe TLP received", tlps.len() << 2);
|
||||
}
|
||||
tlps.clear();
|
||||
}
|
||||
tlp_offs += 4;
|
||||
status >>= 4;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn read_mem_build_request(bytes: &[u8], keep_alive: bool) -> Result<Vec<u8>> {
|
||||
// convert slice into [u32] slice which is 4 times smaller
|
||||
let dwords =
|
||||
unsafe { std::slice::from_raw_parts(bytes.as_ptr() as *const u32, bytes.len() / 4) };
|
||||
|
||||
// tlp buffer constraints
|
||||
if (bytes.len() & 0x3) != 0 || bytes.len() > 4 * 4 + 128 {
|
||||
return Err(Error::Connector("tlp buffer is too large"));
|
||||
}
|
||||
/*
|
||||
if(cbTlp && (txbuf_cb + (cbTlp << 1) + (fFlush ? 8 : 0) >= MAX_SIZE_TX)) {
|
||||
if(!DeviceFPGA_TxTlp(NULL, 0, FALSE, TRUE)) { return FALSE; }
|
||||
}
|
||||
*/
|
||||
|
||||
// TLP_Print
|
||||
|
||||
// create transmit buffer
|
||||
let mut buf = Vec::new();
|
||||
for tlp in dwords.iter() {
|
||||
buf.push(tlp.to_be());
|
||||
buf.push(0x77000000); // TX TLP
|
||||
}
|
||||
|
||||
// TODO: remove this pop in the algorithm
|
||||
if !bytes.is_empty() {
|
||||
buf.pop();
|
||||
buf.push(0x77040000); // TX TLP VALID LAST
|
||||
}
|
||||
|
||||
if keep_alive {
|
||||
buf.push(0xffeeddcc);
|
||||
buf.push(0x77020000);
|
||||
}
|
||||
|
||||
// currently we just flush out every tlp transmission immediately
|
||||
// and not buffer them internally.
|
||||
let byte_buf = buf
|
||||
.iter()
|
||||
.map(|&t| u32::to_le_bytes(t))
|
||||
.collect::<Vec<_>>()
|
||||
.concat();
|
||||
|
||||
Ok(byte_buf.to_vec())
|
||||
}
|
||||
|
||||
pub fn read_mem_into_raw(&mut self, addr: u64, size: u64, device_id: u16) -> Result<()> {
|
||||
|
||||
// TODO: safety checks
|
||||
// TODO: split by page and page align
|
||||
|
||||
let tlp = if addr < size::gb(4) as u64 {
|
||||
TlpReadWrite32::new_read(addr as u32, size as u16, 0x0, device_id).as_bytes().to_vec()
|
||||
} else {
|
||||
TlpReadWrite64::new_read(addr, size as u16, 0x0, device_id).as_bytes().to_vec()
|
||||
};
|
||||
let req = Self::read_mem_build_request(tlp.as_slice(), false)?;
|
||||
|
||||
self.ft60.write_pipe(&req)?;
|
||||
|
||||
std::thread::sleep(std::time::Duration::from_millis(500));
|
||||
|
||||
self.recv_tlps_64(0x1000)?;
|
||||
|
||||
/*
|
||||
let mut readbuf = [0u8; size::kb(128)];
|
||||
let bytes = self.ft60.read_pipe(&mut readbuf)?;
|
||||
|
||||
Self::read_config_parse_response(addr, &readbuf[..bytes], buf, flags)
|
||||
*/
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[allow(clippy::uninit_assumed_init)]
|
||||
fn read_config<T: Pod>(&mut self, addr: u16, flags: u16) -> Result<T> {
|
||||
let mut obj: T = unsafe { MaybeUninit::uninit().assume_init() };
|
||||
self.read_config_into_raw(addr, obj.as_bytes_mut(), flags)?;
|
||||
Ok(obj)
|
||||
}
|
||||
|
||||
fn read_config_build_request(addr: u16, bytes: u16, flags: u16) -> Vec<u8> {
|
||||
let mut res = Vec::new();
|
||||
for a in (addr..addr + bytes).step_by(2) {
|
||||
let mut req = [0u8; 8];
|
||||
req[4] = ((a | (flags & 0x8000)) >> 8) as u8;
|
||||
req[5] = (a & 0xff) as u8;
|
||||
req[6] = (0x10 | (flags & 0x03)) as u8;
|
||||
req[7] = 0x77;
|
||||
res.extend_from_slice(&req);
|
||||
}
|
||||
res
|
||||
}
|
||||
|
||||
fn read_config_parse_response(
|
||||
addr: u16,
|
||||
respbuf: &[u8],
|
||||
outbuf: &mut [u8],
|
||||
flags: u16,
|
||||
) -> Result<()> {
|
||||
let view = respbuf.as_data_view();
|
||||
let mut skip = 0;
|
||||
for i in (0..respbuf.len()).step_by(32) {
|
||||
if i + skip >= respbuf.len() {
|
||||
break;
|
||||
}
|
||||
|
||||
while view.copy::<u32>(i + skip) == 0x55556666 {
|
||||
//trace!("ftdi workaround detected, skipping 4 bytes");
|
||||
skip += 4;
|
||||
if i + skip + 32 > respbuf.len() {
|
||||
return Err(Error::Connector("out of range config read"));
|
||||
}
|
||||
}
|
||||
|
||||
let mut status = view.copy::<u32>(i + skip);
|
||||
if status & 0xf0000000 != 0xe0000000 {
|
||||
trace!("invalid status reply, skipping");
|
||||
}
|
||||
|
||||
trace!("parsing data buffer");
|
||||
for j in 0..7 {
|
||||
let status_flag = (status & 0x0f) == (flags & 0x03) as u32;
|
||||
status >>= 4; // move to next status
|
||||
if !status_flag {
|
||||
//trace!("status source flag does not match source");
|
||||
continue;
|
||||
}
|
||||
|
||||
let data = view.copy::<u32>(i + skip + 4 + j * 4);
|
||||
let mut a = (data as u16).to_be(); // only enforce a byteswap if we are on le
|
||||
a -= (flags & 0x8000) + addr;
|
||||
if a >= outbuf.len() as u16 {
|
||||
trace!("address data out of range, skipping");
|
||||
continue;
|
||||
}
|
||||
|
||||
if a == outbuf.len() as u16 - 1 {
|
||||
outbuf[a as usize] = ((data >> 16) & 0xff) as u8;
|
||||
} else {
|
||||
let b = (((data >> 16) & 0xffff) as u16).to_le_bytes();
|
||||
outbuf[a as usize] = b[0];
|
||||
outbuf[a as usize + 1] = b[1];
|
||||
}
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn read_config_into_raw(&mut self, addr: u16, buf: &mut [u8], flags: u16) -> Result<()> {
|
||||
if buf.is_empty() || buf.len() > size::kb(4) || addr > size::kb(4) as u16 {
|
||||
return Err(Error::Connector("invalid config address requested"));
|
||||
}
|
||||
|
||||
let req = Self::read_config_build_request(addr, buf.len() as u16, flags);
|
||||
|
||||
self.ft60.write_pipe(&req)?;
|
||||
|
||||
let mut readbuf = [0u8; size::kb(128)];
|
||||
let bytes = self.ft60.read_pipe(&mut readbuf)?;
|
||||
|
||||
Self::read_config_parse_response(addr, &readbuf[..bytes], buf, flags)
|
||||
}
|
||||
|
||||
fn write_config<T: Pod>(&mut self, addr: u16, obj: T, flags: u16) -> Result<()> {
|
||||
self.write_config_raw(addr, obj.as_bytes(), flags)
|
||||
}
|
||||
|
||||
fn write_config_build_request(addr: u16, buf: &[u8], flags: u16) -> Result<Vec<u8>> {
|
||||
if buf.is_empty() || buf.len() > 0x200 || addr > size::kb(4) as u16 {
|
||||
return Err(Error::Connector("invalid config address to write"));
|
||||
}
|
||||
|
||||
let mut outbuf = [0u8; 0x800];
|
||||
let mut ptr = 0;
|
||||
for i in (0..buf.len()).step_by(2) {
|
||||
let a = (addr + i as u16) | (flags & 0x8000);
|
||||
outbuf[ptr] = buf[i as usize]; // byte_value_addr
|
||||
outbuf[ptr + 1] = if buf.len() == i + 1 {
|
||||
0
|
||||
} else {
|
||||
buf[i as usize + 1]
|
||||
}; // byte_value_addr + 1
|
||||
outbuf[ptr + 2] = 0xFF; // byte_mask_addr
|
||||
outbuf[ptr + 3] = if buf.len() == i + 1 { 0 } else { 0xFF }; // byte_mask_addr + 1
|
||||
outbuf[ptr + 4] = (a >> 8) as u8; // addr_high = bit[6:0], write_regbank = bit[7]
|
||||
outbuf[ptr + 5] = (a & 0xFF) as u8; // addr_low
|
||||
outbuf[ptr + 6] = (0x20 | (flags & 0x03)) as u8; // target = bit[0:1], read = bit[4], write = bit[5]
|
||||
outbuf[ptr + 7] = 0x77; // MAGIC 0x77
|
||||
ptr += 8;
|
||||
}
|
||||
|
||||
Ok(outbuf[..ptr].to_vec())
|
||||
}
|
||||
|
||||
fn write_config_raw(&mut self, addr: u16, buf: &[u8], flags: u16) -> Result<()> {
|
||||
let outbuf = Self::write_config_build_request(addr, buf, flags)?;
|
||||
self.ft60.write_pipe(&outbuf)
|
||||
}
|
||||
|
||||
fn write_config_ex_build_request(
|
||||
addr: u16,
|
||||
buf: [u8; 2],
|
||||
mask: [u8; 2],
|
||||
flags: u16,
|
||||
) -> Result<[u8; 8]> {
|
||||
let a = (addr as u16) | (flags & 0x8000);
|
||||
Ok([
|
||||
buf[0],
|
||||
buf[1],
|
||||
mask[0],
|
||||
mask[1],
|
||||
(a >> 8) as u8, // addr_high
|
||||
(a & 0xFF) as u8, // addr_low
|
||||
(0x20 | (flags & 0x03)) as u8, // target = bit[0:1], read = bit[4], write = bit[5]
|
||||
0x77, // MAGIC 0x77
|
||||
])
|
||||
}
|
||||
|
||||
fn write_config_ex_raw(
|
||||
&mut self,
|
||||
addr: u16,
|
||||
buf: [u8; 2],
|
||||
mask: [u8; 2],
|
||||
flags: u16,
|
||||
) -> Result<()> {
|
||||
let outbuf = Self::write_config_ex_build_request(addr, buf, mask, flags)?;
|
||||
self.ft60.write_pipe(&outbuf)
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use core::mem::size_of;
|
||||
|
||||
#[test]
|
||||
fn test_struct_sizes() {
|
||||
assert_eq!(size_of::<PhyConfigWr>(), 2);
|
||||
assert_eq!(size_of::<PhyConfigRd>(), 4);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_read_build_request() {
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x0008,
|
||||
1,
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x13, 0x77]
|
||||
);
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x0009,
|
||||
1,
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x13, 0x77]
|
||||
);
|
||||
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x0008,
|
||||
2,
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x11, 0x77]
|
||||
);
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x0000,
|
||||
2,
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x80, 0x0, 0x11, 0x77]
|
||||
);
|
||||
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x0016,
|
||||
2,
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x80, 0x16, 0x11, 0x77]
|
||||
);
|
||||
assert_eq!(
|
||||
Device::read_config_build_request(
|
||||
0x000a,
|
||||
4,
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY
|
||||
),
|
||||
[0x0, 0x0, 0x0, 0x0, 0x0, 0xA, 0x11, 0x77, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC, 0x11, 0x77]
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_version_major() {
|
||||
let mut version_major = 0u8;
|
||||
Device::read_config_parse_response(
|
||||
0x0008,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 243, 255, 255, 239, 0, 8, 4, 2, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
version_major.as_bytes_mut(),
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(version_major, 4);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_version_minor() {
|
||||
let mut version_minor = 0u8;
|
||||
Device::read_config_parse_response(
|
||||
0x0009,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 243, 255, 255, 239, 0, 9, 2, 1, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
version_minor.as_bytes_mut(),
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(version_minor, 2);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_fpga_id() {
|
||||
let mut fpga_id = 0u8;
|
||||
Device::read_config_parse_response(
|
||||
0x000a,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 243, 255, 255, 239, 0, 10, 1, 0, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
fpga_id.as_bytes_mut(),
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(fpga_id, 1);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_device_id() {
|
||||
let mut fpga_id = 0u8;
|
||||
Device::read_config_parse_response(
|
||||
0x000a,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 243, 255, 255, 239, 0, 10, 1, 0, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
fpga_id.as_bytes_mut(),
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(fpga_id, 1);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_phy_wr() {
|
||||
let mut wr = 0u16;
|
||||
Device::read_config_parse_response(
|
||||
0x0016,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 241, 255, 255, 239, 128, 22, 72, 0, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
wr.as_bytes_mut(),
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(wr, 0x48);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_config_parse_phy_rd() {
|
||||
let mut rd = 0u32;
|
||||
Device::read_config_parse_response(
|
||||
0x000a,
|
||||
&[
|
||||
102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102,
|
||||
85, 85, 17, 255, 255, 239, 0, 10, 25, 8, 0, 12, 28, 0, 255, 255, 255, 255, 255,
|
||||
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
||||
],
|
||||
rd.as_bytes_mut(),
|
||||
FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(rd, 0x1C0819);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn write_config_inactivity_timer() {
|
||||
let inactivity_timer = 0x000186a0u32; // set inactivity timer to 1ms (0x0186a0 * 100MHz) [only later activated on UDP bitstreams]
|
||||
let outbuf = Device::write_config_build_request(
|
||||
0x0008,
|
||||
inactivity_timer.as_bytes(),
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(
|
||||
outbuf,
|
||||
[160, 134, 255, 255, 128, 8, 35, 119, 1, 0, 255, 255, 128, 10, 35, 119]
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn write_config_core_reset() {
|
||||
let code: [u8; 2] = [0x00, 0x80];
|
||||
let outbuf = Device::write_config_ex_build_request(
|
||||
0x0002,
|
||||
code,
|
||||
code,
|
||||
FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE,
|
||||
)
|
||||
.unwrap();
|
||||
assert_eq!(outbuf, [0, 128, 0, 128, 128, 2, 35, 119,]);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_read_mem32() {
|
||||
let tlp = TlpReadWrite32::new_read(0x6000, 0x123, 0x80, 17);
|
||||
assert_eq!(
|
||||
Device::read_mem_build_request(&tlp.as_bytes(), false).unwrap(),
|
||||
[0, 0, 0, 72, 0, 0, 0, 119, 0, 17, 128, 255, 0, 0, 0, 119, 0, 0, 96, 0, 0, 0, 4, 119]
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_read_mem64() {
|
||||
let tlp = TlpReadWrite64::new_read(size::gb(4) as u64 + 0x6000, 0x123, 0x80, 17);
|
||||
assert_eq!(
|
||||
Device::read_mem_build_request(&tlp.as_bytes(), false).unwrap(),
|
||||
[
|
||||
32, 0, 0, 72, 0, 0, 0, 119, 0, 17, 128, 255, 0, 0, 0, 119, 0, 0, 0, 1, 0, 0, 0,
|
||||
119, 0, 0, 96, 0, 0, 0, 4, 119
|
||||
]
|
||||
);
|
||||
}
|
||||
}
|
||||
@ -1,181 +0,0 @@
|
||||
use c2rust_bitfields::*;
|
||||
use dataview::{DataView, Pod};
|
||||
|
||||
const TLP_READ_32: u8 = 0x00;
|
||||
const TLP_READ_64: u8 = 0x20;
|
||||
|
||||
const fn pack_bits4(first: u8, second: u8) -> u8 {
|
||||
(first & ((1 << 4) - 1)) + ((second & ((1 << 4) - 1)) << 4)
|
||||
}
|
||||
|
||||
#[repr(C, align(1))]
|
||||
#[derive(BitfieldStruct, Pod)]
|
||||
pub struct TlpHeader {
|
||||
#[bitfield(name = "len_tlps", ty = "libc::uint16_t", bits = "0..=9")]
|
||||
#[bitfield(name = "at", ty = "libc::uint16_t", bits = "10..=11")]
|
||||
#[bitfield(name = "attr", ty = "libc::uint16_t", bits = "12..=13")]
|
||||
#[bitfield(name = "ep", ty = "libc::uint16_t", bits = "14..=14")]
|
||||
#[bitfield(name = "td", ty = "libc::uint16_t", bits = "15..=15")]
|
||||
#[bitfield(name = "r1", ty = "libc::uint8_t", bits = "16..=19")]
|
||||
#[bitfield(name = "tc", ty = "libc::uint8_t", bits = "20..=22")]
|
||||
#[bitfield(name = "r2", ty = "libc::uint8_t", bits = "23..=23")]
|
||||
#[bitfield(name = "ty", ty = "libc::uint8_t", bits = "24..=31")]
|
||||
buffer: [u8; 4],
|
||||
}
|
||||
const _: [(); core::mem::size_of::<TlpHeader>()] = [(); 4];
|
||||
|
||||
impl TlpHeader {
|
||||
pub fn new(ty: u8, len_tlps: u16) -> Self {
|
||||
let mut h = Self::zeroed();
|
||||
h.set_ty(ty);
|
||||
if len_tlps < 0x1000 {
|
||||
// shift length
|
||||
h.set_len_tlps(len_tlps / 4);
|
||||
} else {
|
||||
// max length
|
||||
h.set_len_tlps(len_tlps);
|
||||
}
|
||||
h
|
||||
}
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[derive(Pod)]
|
||||
pub struct TlpReadWrite32 {
|
||||
header: TlpHeader,
|
||||
be: u8,
|
||||
tag: u8,
|
||||
requester_id: u16,
|
||||
address: u32,
|
||||
}
|
||||
const _: [(); core::mem::size_of::<TlpReadWrite32>()] = [(); 0xC];
|
||||
|
||||
#[allow(unused)]
|
||||
impl TlpReadWrite32 {
|
||||
pub fn new_read(address: u32, len: u16, tag: u8, requester_id: u16) -> Self {
|
||||
Self {
|
||||
header: TlpHeader::new(TLP_READ_32, len),
|
||||
be: pack_bits4(0xF, 0xF),
|
||||
tag,
|
||||
requester_id,
|
||||
address,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_be(&mut self, first: u8, second: u8) {
|
||||
self.be = pack_bits4(first, second);
|
||||
}
|
||||
|
||||
pub fn set_tag(&mut self, tag: u8) {
|
||||
self.tag = tag;
|
||||
}
|
||||
|
||||
pub fn set_requester_id(&mut self, id: u16) {
|
||||
self.requester_id = id;
|
||||
}
|
||||
|
||||
pub fn set_address(&mut self, address: u32) {
|
||||
self.address = address;
|
||||
}
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[derive(Pod)]
|
||||
pub struct TlpReadWrite64 {
|
||||
header: TlpHeader,
|
||||
be: u8,
|
||||
tag: u8,
|
||||
requester_id: u16,
|
||||
address_high: u32,
|
||||
address_low: u32,
|
||||
}
|
||||
const _: [(); core::mem::size_of::<TlpReadWrite64>()] = [(); 0x10];
|
||||
|
||||
#[allow(unused)]
|
||||
impl TlpReadWrite64 {
|
||||
pub fn new_read(address: u64, len: u16, tag: u8, requester_id: u16) -> Self {
|
||||
Self {
|
||||
header: TlpHeader::new(TLP_READ_64, len),
|
||||
be: pack_bits4(0xF, 0xF),
|
||||
tag,
|
||||
requester_id,
|
||||
address_high: (address >> 32) as u32,
|
||||
address_low: address as u32,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_be(&mut self, first: u8, second: u8) {
|
||||
self.be = pack_bits4(first, second);
|
||||
}
|
||||
|
||||
pub fn set_tag(&mut self, tag: u8) {
|
||||
self.tag = tag;
|
||||
}
|
||||
|
||||
pub fn set_requester_id(&mut self, id: u16) {
|
||||
self.requester_id = id;
|
||||
}
|
||||
|
||||
pub fn set_address(&mut self, address: u64) {
|
||||
self.address_high = (address >> 32) as u32;
|
||||
self.address_low = address as u32;
|
||||
}
|
||||
}
|
||||
|
||||
/// Tlp Packet - Completion with Data
|
||||
#[repr(C, align(1))]
|
||||
#[derive(BitfieldStruct, Pod)]
|
||||
pub struct TlpCplD {
|
||||
header: TlpHeader,
|
||||
#[bitfield(name = "byte_count", ty = "libc::uint16_t", bits = "0..=11")]
|
||||
#[bitfield(name = "attr", ty = "libc::uint16_t", bits = "12..=12")]
|
||||
#[bitfield(name = "ep", ty = "libc::uint16_t", bits = "13..=15")]
|
||||
buffer1: [u8; 2],
|
||||
completer_id: u16,
|
||||
#[bitfield(name = "lower_addr", ty = "libc::uint8_t", bits = "0..=6")]
|
||||
#[bitfield(name = "r1", ty = "libc::uint8_t", bits = "7..=7")]
|
||||
buffer2: [u8; 1],
|
||||
tag: u8,
|
||||
requester_id: u16,
|
||||
}
|
||||
//const _: [(); core::mem::size_of::<TlpCplD>()] = [(); 0x10];
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::{pack_bits4, TlpHeader, TlpReadWrite32, TlpReadWrite64, TLP_READ_32, TLP_READ_64};
|
||||
use dataview::Pod;
|
||||
use memflow::size;
|
||||
|
||||
#[test]
|
||||
fn test_pack_bits4() {
|
||||
assert_eq!(pack_bits4(0xA, 0xB), 0xBA);
|
||||
assert_eq!(pack_bits4(0xAB, 0xCD), 0xDB);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_header32() {
|
||||
let header = TlpHeader::new(TLP_READ_32, 0x123);
|
||||
assert_eq!(header.as_bytes(), &[72, 0, 0, 0])
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_header64() {
|
||||
let header = TlpHeader::new(TLP_READ_64, 0x123);
|
||||
assert_eq!(header.as_bytes(), &[72, 0, 0, 32])
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_tlp_rw32() {
|
||||
let tlp = TlpReadWrite32::new_read(0x6000, 0x123, 0x80, 17);
|
||||
assert_eq!(tlp.as_bytes(), &[72, 0, 0, 0, 255, 128, 17, 0, 0, 96, 0, 0])
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_tlp_rw64() {
|
||||
let tlp = TlpReadWrite64::new_read(size::gb(4) as u64 + 0x6000, 0x123, 0x80, 17);
|
||||
assert_eq!(
|
||||
tlp.as_bytes(),
|
||||
&[72, 0, 0, 32, 255, 128, 17, 0, 1, 0, 0, 0, 0, 96, 0, 0]
|
||||
)
|
||||
}
|
||||
}
|
||||
@ -1,200 +0,0 @@
|
||||
/// This module provides a wrapper around libusb to communicate with a FT60x chip directly.
|
||||
/// The main interface will be through the chip configuration and read/write pipe functions.
|
||||
mod chip;
|
||||
pub use chip::{ChannelConfig, FifoMode, OptionalFeatureSupport};
|
||||
|
||||
use rusb::{
|
||||
request_type, DeviceHandle, DeviceList, Direction, GlobalContext, Recipient, RequestType,
|
||||
};
|
||||
|
||||
use core::mem::size_of;
|
||||
use core::time::Duration;
|
||||
|
||||
use log::{info, trace};
|
||||
|
||||
use memflow::error::{Error, Result};
|
||||
|
||||
use dataview::Pod;
|
||||
|
||||
pub const FTDI_VENDOR_ID: u16 = 0x0403;
|
||||
pub const FTDI_FT60X_PRODUCT_ID: u16 = 0x601f;
|
||||
|
||||
// TODO: enum?
|
||||
pub const FTDI_COMMUNICATION_INTERFACE: u8 = 0x00;
|
||||
pub const FTDI_DATA_INTERFACE: u8 = 0x01;
|
||||
|
||||
// TODO: enum?
|
||||
pub const FTDI_ENDPOINT_SESSION_OUT: u8 = 0x01;
|
||||
pub const FTDI_ENDPOINT_OUT: u8 = 0x02;
|
||||
pub const FTDI_ENDPOINT_IN: u8 = 0x82;
|
||||
|
||||
pub struct FT60x {
|
||||
handle: DeviceHandle<GlobalContext>,
|
||||
}
|
||||
|
||||
impl FT60x {
|
||||
/// Tries to open a usb connection to a FT60x chip connected via libusb.
|
||||
// TODO: handle multiple devices at the same time
|
||||
pub fn new() -> Result<Self> {
|
||||
let (dev, desc) = DeviceList::new()
|
||||
.map_err(|_| Error::Connector("unable to get usb device list"))?
|
||||
.iter()
|
||||
.filter_map(|dev| match dev.device_descriptor() {
|
||||
Ok(desc) => Some((dev, desc)),
|
||||
Err(_) => None,
|
||||
})
|
||||
.find(|(_dev, desc)| {
|
||||
desc.vendor_id() == FTDI_VENDOR_ID && desc.product_id() == FTDI_FT60X_PRODUCT_ID
|
||||
})
|
||||
.ok_or_else(|| Error::Connector("unable to find ftdi device"))?;
|
||||
|
||||
info!(
|
||||
"found FTDI device: {}:{} (bus {}, device {})",
|
||||
desc.vendor_id(),
|
||||
desc.product_id(),
|
||||
dev.bus_number(),
|
||||
dev.address()
|
||||
);
|
||||
|
||||
// open handle and reset chip
|
||||
let mut handle = dev
|
||||
.open()
|
||||
.map_err(|_| Error::Connector("unable to open ftdi usb device"))?;
|
||||
handle
|
||||
.reset()
|
||||
.map_err(|_| Error::Connector("unable to reset ftdi device"))?;
|
||||
|
||||
/*
|
||||
let manufacturer = handle
|
||||
.read_string_descriptor_ascii(desc.manufacturer_string_index().unwrap_or_default())
|
||||
.map_err(|_| Error::Connector("unable to read ftdi manufacturer name"))?;
|
||||
let product = handle
|
||||
.read_string_descriptor_ascii(desc.product_string_index().unwrap_or_default())
|
||||
.map_err(|_| Error::Connector("unable to read ftdi product name"))?;
|
||||
let serial = handle
|
||||
.read_string_descriptor_ascii(desc.serial_number_string_index().unwrap_or_default())
|
||||
.map_err(|_| Error::Connector("unable to read ftdi serial number"))?;
|
||||
info!(
|
||||
"device: manufacturer={} product={} serial={}",
|
||||
manufacturer, product, serial
|
||||
);
|
||||
*/
|
||||
|
||||
// check driver state
|
||||
if handle
|
||||
.kernel_driver_active(FTDI_COMMUNICATION_INTERFACE)
|
||||
.map_err(|_| Error::Connector("ftdi driver check failed"))?
|
||||
{
|
||||
return Err(Error::Connector(
|
||||
"ftdi driver is already active on FTDI_COMMUNICATION_INTERFACE",
|
||||
));
|
||||
}
|
||||
info!("ftdi driver is not active on FTDI_COMMUNICATION_INTERFACE");
|
||||
|
||||
if handle
|
||||
.kernel_driver_active(FTDI_DATA_INTERFACE)
|
||||
.map_err(|_| Error::Connector("ftdi driver check failed"))?
|
||||
{
|
||||
return Err(Error::Connector(
|
||||
"ftdi driver is already active on FTDI_DATA_INTERFACE",
|
||||
));
|
||||
}
|
||||
info!("ftdi driver is not active on FTDI_DATA_INTERFACE");
|
||||
|
||||
// claim interfaces
|
||||
handle
|
||||
.claim_interface(FTDI_COMMUNICATION_INTERFACE)
|
||||
.map_err(|_| Error::Connector("unable to claim FTDI_COMMUNICATION_INTERFACE"))?;
|
||||
handle
|
||||
.claim_interface(FTDI_DATA_INTERFACE)
|
||||
.map_err(|_| Error::Connector("unable to claim FTDI_DATA_INTERFACE"))?;
|
||||
|
||||
Ok(Self { handle })
|
||||
}
|
||||
|
||||
pub fn abort_pipe(&mut self, pipe_id: u8) -> Result<()> {
|
||||
// dummy function, only used for ftdi compat
|
||||
trace!("abort_pipe: {}", pipe_id);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn set_suspend_timeout(&mut self, timeout: Duration) -> Result<()> {
|
||||
// dummy function, only used for ftdi compat
|
||||
trace!("set_suspend_timeout: {:?}", timeout);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Retrieves the FT60x chip configuration
|
||||
pub fn config(&mut self) -> Result<chip::Config> {
|
||||
let mut buf = vec![0u8; size_of::<chip::Config>()];
|
||||
self.handle
|
||||
.read_control(
|
||||
request_type(Direction::In, RequestType::Vendor, Recipient::Device),
|
||||
0xCF,
|
||||
1,
|
||||
0,
|
||||
&mut buf,
|
||||
Duration::from_millis(1000),
|
||||
)
|
||||
.map_err(|_| Error::Connector("unable to get ft60x config"))?;
|
||||
|
||||
// dataview buf to struct
|
||||
let view = buf.as_data_view();
|
||||
Ok(view.copy::<chip::Config>(0))
|
||||
}
|
||||
|
||||
/// Writes the FT60x chip configuration
|
||||
pub fn set_config(&mut self, conf: &chip::Config) -> Result<()> {
|
||||
let bytes = self
|
||||
.handle
|
||||
.write_control(
|
||||
request_type(Direction::Out, RequestType::Vendor, Recipient::Device),
|
||||
0xCF,
|
||||
0,
|
||||
0,
|
||||
conf.as_bytes(),
|
||||
Duration::from_millis(1000),
|
||||
)
|
||||
.map_err(|_| Error::Connector("unable to set ft60x config"))?;
|
||||
if bytes == size_of::<chip::Config>() {
|
||||
Ok(())
|
||||
} else {
|
||||
Err(Error::Connector("unable to set ft60x config"))
|
||||
}
|
||||
}
|
||||
|
||||
/// Write to the ft60x chip
|
||||
pub fn write_pipe(&mut self, data: &[u8]) -> Result<()> {
|
||||
self.write_bulk_raw(FTDI_ENDPOINT_OUT, data)
|
||||
}
|
||||
|
||||
/// Read from the ft60x chip
|
||||
pub fn read_pipe(&mut self, data: &mut [u8]) -> Result<usize> {
|
||||
self.send_read_request(data.len() as u32)?;
|
||||
self.handle
|
||||
.read_bulk(FTDI_ENDPOINT_IN, data, Duration::from_millis(1000))
|
||||
.map_err(|_| Error::Connector("unable to read from ft60x"))
|
||||
}
|
||||
|
||||
/// Sends a ControlRequest to issue a read with a given size
|
||||
fn send_read_request(&mut self, len: u32) -> Result<()> {
|
||||
let req = chip::ControlRequest::new(1, FTDI_ENDPOINT_IN, 1, len);
|
||||
self.write_bulk_raw(FTDI_ENDPOINT_SESSION_OUT, req.as_bytes())
|
||||
}
|
||||
|
||||
/// Does a raw bulk write to the chip and validates the sent size
|
||||
fn write_bulk_raw(&self, endpoint: u8, buf: &[u8]) -> Result<()> {
|
||||
// TODO: customizable write_bulk timeout
|
||||
let bytes = self
|
||||
.handle
|
||||
.write_bulk(endpoint, buf, Duration::from_millis(1000))
|
||||
.map_err(|_| Error::Connector("unable to write to ft60x"))?;
|
||||
if bytes == buf.len() {
|
||||
Ok(())
|
||||
} else {
|
||||
Err(Error::Connector(
|
||||
"unable to write the entire buffer to the ft60x",
|
||||
))
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,112 +0,0 @@
|
||||
use dataview::Pod;
|
||||
|
||||
/// Chip configuration - FIFO Mode
|
||||
#[allow(unused)]
|
||||
pub enum FifoMode {
|
||||
Mode245 = 0,
|
||||
Mode600 = 1,
|
||||
Max = 2,
|
||||
}
|
||||
|
||||
/// Chip configuration - Channel Configuration
|
||||
#[allow(unused)]
|
||||
pub enum ChannelConfig {
|
||||
Config4 = 0,
|
||||
Config2 = 1,
|
||||
Config1 = 2,
|
||||
Config1OutPipe = 3,
|
||||
Config1InPipe = 4,
|
||||
Max = 5,
|
||||
}
|
||||
|
||||
/// Chip configuration - Optional Feature Support
|
||||
#[allow(unused)]
|
||||
pub enum OptionalFeatureSupport {
|
||||
DisableAll = 0,
|
||||
EnableBatteryCharging = 1,
|
||||
DisableCancelSessionUnderrun = 2,
|
||||
EnableNotificationMessageInch1 = 4,
|
||||
EnableNotificationMessageInch2 = 8,
|
||||
EnableNotificationMessageInch3 = 0x10,
|
||||
EnableNotificationMessageInch4 = 0x20,
|
||||
EnableNotificationMessageInchAll = 0x3C,
|
||||
DisableUnderrunInch1 = 0x1 << 6,
|
||||
DisableUnderrunInch2 = 0x1 << 7,
|
||||
DisableUnderrunInch3 = 0x1 << 8,
|
||||
DisableUnderrunInch4 = 0x1 << 9,
|
||||
DisableUnderrunInchAll = 0xF << 6,
|
||||
}
|
||||
|
||||
/// Chip configuration - Config structure
|
||||
#[repr(C)]
|
||||
#[derive(Clone, Pod)]
|
||||
pub struct Config {
|
||||
// Device Descriptor
|
||||
pub vendor_id: i16,
|
||||
pub product_id: i16,
|
||||
|
||||
// String Descriptors
|
||||
pub string_descriptors: [i8; 128],
|
||||
|
||||
// Configuration Descriptor
|
||||
reserved1: i8,
|
||||
pub power_attributes: i8,
|
||||
pub power_consumption: i16,
|
||||
|
||||
// Data Transfer Configuration
|
||||
reserved2: i8,
|
||||
pub fifo_clock: i8,
|
||||
pub fifo_mode: i8,
|
||||
pub channel_config: i8,
|
||||
|
||||
// Optional Feature Support
|
||||
pub optional_feature_support: i16,
|
||||
pub battery_charging_gpio_config: i8,
|
||||
pub flash_eeprom_detection: i8, // Read-only
|
||||
|
||||
// MSIO and GPIO Configuration
|
||||
pub msio_control: u32,
|
||||
pub gpio_control: u32,
|
||||
}
|
||||
const _: [(); core::mem::size_of::<Config>()] = [(); 0x98];
|
||||
|
||||
#[repr(C, packed)]
|
||||
#[derive(Copy, Clone, Pod)]
|
||||
pub struct ControlRequest {
|
||||
pub idx: u32,
|
||||
pub pipe: u8,
|
||||
pub cmd: u8,
|
||||
unknown1: u8,
|
||||
unknown2: u8,
|
||||
pub len: u32,
|
||||
unknown3: u32,
|
||||
unknown4: u32,
|
||||
}
|
||||
const _: [(); core::mem::size_of::<ControlRequest>()] = [(); 0x14];
|
||||
|
||||
impl ControlRequest {
|
||||
pub fn new(idx: u32, pipe: u8, cmd: u8, len: u32) -> Self {
|
||||
Self {
|
||||
idx,
|
||||
pipe,
|
||||
cmd,
|
||||
unknown1: 0,
|
||||
unknown2: 0,
|
||||
len,
|
||||
unknown3: 0,
|
||||
unknown4: 0,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use core::mem::size_of;
|
||||
|
||||
#[test]
|
||||
fn test_struct_sizes() {
|
||||
assert_eq!(size_of::<Config>(), 0x98);
|
||||
assert_eq!(size_of::<ControlRequest>(), 0x14);
|
||||
}
|
||||
}
|
||||
@ -1,161 +0,0 @@
|
||||
mod fpga;
|
||||
mod ft60x;
|
||||
|
||||
//TODO: move?
|
||||
use fpga::tlps::*;
|
||||
|
||||
use log::{info, warn};
|
||||
|
||||
use fpga::{PhyConfigRd, PhyConfigWr};
|
||||
|
||||
use memflow::connector::ConnectorArgs;
|
||||
use memflow::*;
|
||||
use memflow_derive::connector;
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum PcieGen {
|
||||
Gen1 = 0,
|
||||
Gen2 = 1,
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
pub struct PciLeech {
|
||||
device: fpga::Device,
|
||||
|
||||
version_major: u8,
|
||||
version_minor: u8,
|
||||
fpga_id: u8,
|
||||
device_id: u16,
|
||||
|
||||
phy_wr: PhyConfigWr,
|
||||
phy_rd: PhyConfigRd,
|
||||
}
|
||||
|
||||
impl PciLeech {
|
||||
pub fn new() -> Result<Self> {
|
||||
let mut device = fpga::Device::new()?;
|
||||
device.clear_pipe()?;
|
||||
|
||||
let version = device.read_version()?;
|
||||
if version.0 != 4 {
|
||||
return Err(Error::Connector("only pcileech 4.x devices are supported"));
|
||||
}
|
||||
|
||||
device.write_inactivity_timer()?;
|
||||
|
||||
let device_id = device.read_devid()?;
|
||||
if device_id.1 == 0 {
|
||||
return Err(Error::Connector("fpga did not find a valid pcie device id"));
|
||||
}
|
||||
|
||||
let (wr, rd) = device.get_phy()?;
|
||||
|
||||
device.print_registers().ok();
|
||||
|
||||
Ok(Self {
|
||||
device,
|
||||
|
||||
version_major: version.0,
|
||||
version_minor: version.1,
|
||||
fpga_id: device_id.0,
|
||||
device_id: device_id.1,
|
||||
|
||||
phy_wr: wr,
|
||||
phy_rd: rd,
|
||||
})
|
||||
}
|
||||
|
||||
pub fn pcie_link_width(&self) -> u8 {
|
||||
match self.phy_rd.pl_sel_lnk_width() {
|
||||
0 => 1,
|
||||
1 => 2,
|
||||
2 => 4,
|
||||
3 => 8,
|
||||
_ => 0, // invalid
|
||||
}
|
||||
}
|
||||
|
||||
pub fn pcie_gen(&self) -> PcieGen {
|
||||
match self.phy_rd.pl_sel_lnk_rate() {
|
||||
0 => PcieGen::Gen1,
|
||||
1 => PcieGen::Gen2,
|
||||
_ => panic!("invalid sel_lnk_rate"),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_pcie_gen(&mut self, gen: PcieGen) -> Result<()> {
|
||||
let genb = gen as u8;
|
||||
if genb == self.phy_rd.pl_sel_lnk_rate() {
|
||||
info!("requested pcie gen already set.");
|
||||
return Ok(());
|
||||
}
|
||||
|
||||
if genb != 0 && self.phy_rd.pl_link_gen2_cap() == 0 {
|
||||
warn!("pcie gen2 is not supported by the fpga configuration");
|
||||
return Err(Error::Connector(
|
||||
"pcie gen2 is not supported by the fpga configuration",
|
||||
));
|
||||
}
|
||||
|
||||
// update config
|
||||
self.phy_wr.set_pl_directed_link_auton(1);
|
||||
self.phy_wr.set_pl_directed_link_speed(genb);
|
||||
self.phy_wr.set_pl_directed_link_change(2);
|
||||
self.device.set_phy_wr(&self.phy_wr)?;
|
||||
|
||||
// poll config update
|
||||
for _ in 0..32 {
|
||||
if let Ok(rd) = self.device.get_phy_rd() {
|
||||
if rd.pl_directed_change_done() == 1 {
|
||||
info!("fpga changes successfully applied");
|
||||
self.phy_rd = rd;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// reset config
|
||||
self.phy_wr.set_pl_directed_link_auton(0);
|
||||
self.phy_wr.set_pl_directed_link_speed(0);
|
||||
self.phy_wr.set_pl_directed_link_change(0);
|
||||
self.device.set_phy_wr(&self.phy_wr)?;
|
||||
|
||||
// update internal state
|
||||
self.phy_wr = self.device.get_phy_wr()?;
|
||||
self.phy_rd = self.device.get_phy_rd()?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
// test read functions
|
||||
pub fn test_read(&mut self) -> Result<()> {
|
||||
// create read request
|
||||
self.device.read_mem_into_raw(0x1000, 0x1000, self.device_id);
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl PhysicalMemory for PciLeech {
|
||||
fn phys_read_raw_list(&mut self, _data: &mut [PhysicalReadData]) -> Result<()> {
|
||||
Err(Error::Connector(
|
||||
"memflow_pcileech::phys_read_iter not implemented",
|
||||
))
|
||||
}
|
||||
|
||||
fn phys_write_raw_list(&mut self, _data: &[PhysicalWriteData]) -> Result<()> {
|
||||
Err(Error::Connector(
|
||||
"memflow_pcileech::phys_write_iter not implemented",
|
||||
))
|
||||
}
|
||||
|
||||
fn metadata(&self) -> PhysicalMemoryMetadata {
|
||||
panic!()
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: handle args properly
|
||||
/// Creates a new Pcileech Connector instance.
|
||||
#[connector(name = "pcileech")]
|
||||
pub fn create_connector(_args: &ConnectorArgs) -> Result<PciLeech> {
|
||||
PciLeech::new()
|
||||
}
|
||||
Loading…
Reference in New Issue